Update VHDL and Python files for improved functionality and performance
- Updated the date in the diligent_jstk_wrapper.vhd file. - Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time. - Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication. - Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors. - Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.
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@@ -1,11 +1,24 @@
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import serial
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import serial.tools.list_ports
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import time
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# CONFIGURAZIONE
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PORT = 'COM4' # Cambia con la tua porta: es. 'COM3' su Windows o '/dev/ttyUSB0' su Linux
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BASYS3_PID = 0x6010
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BASYS3_VID = 0x0403
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BAUDRATE = 115200 # Imposta la tua velocità
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CHUNK_SIZE = 4 # 4 byte per riga
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# Ricerca automatica della porta Basys3
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dev = ""
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for port in serial.tools.list_ports.comports():
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if (port.vid == BASYS3_VID and port.pid == BASYS3_PID):
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dev = port.device
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if not dev:
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raise RuntimeError("Basys 3 Not Found!")
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PORT = dev
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def receive_mode(ser):
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print("Modalità ricezione. Premi Ctrl+C per uscire.\n")
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while True:
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@@ -41,16 +54,20 @@ def send_mode(ser):
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try:
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mode = ""
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while mode not in ["r", "s"]:
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mode = input("Vuoi ricevere (r) o inviare (s) dati? [r/s]: ").strip().lower()
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while mode not in ["r", "s", "4"]:
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mode = input("Vuoi ricevere (r), inviare (s) ? [r/s]: ").strip().lower()
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ser = serial.Serial(PORT, BAUDRATE, timeout=1)
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print(f"Aperta porta seriale: {PORT} a {BAUDRATE} baud.\n")
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if mode == "r":
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receive_mode(ser)
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else:
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elif mode == "s":
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send_mode(ser)
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else:
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print("Selezione non valida. Uscita...")
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ser.close()
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exit(1)
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except KeyboardInterrupt:
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print("\nChiusura programma...")
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