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Update VHDL and Python files for improved functionality and performance

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- Updated the date in the diligent_jstk_wrapper.vhd file.
- Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time.
- Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication.
- Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors.
- Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.
This commit is contained in:
Davide Cavagnola
2025-05-15 16:46:09 +02:00
parent aa8d8f3c7c
commit c3967c3124
6 changed files with 495 additions and 192 deletions
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69
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -5,7 +5,7 @@
"device": "xc7a35tcpg236-1", "device": "xc7a35tcpg236-1",
"name": "diligent_jstk", "name": "diligent_jstk",
"rev_ctrl_bd_flag": "RevCtrlBdOff", "rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None", "synth_flow_mode": "Hierarchical",
"tool_version": "2020.2", "tool_version": "2020.2",
"validated": "true" "validated": "true"
}, },
@@ -15,7 +15,8 @@
"AXI4Stream_UART_0": "", "AXI4Stream_UART_0": "",
"jstk_uart_bridge_0": "", "jstk_uart_bridge_0": "",
"axi4stream_spi_master_0": "", "axi4stream_spi_master_0": "",
"digilent_jstk2_0": "" "digilent_jstk2_0": "",
"system_ila_0": ""
}, },
"interface_ports": { "interface_ports": {
"usb_uart": { "usb_uart": {
@@ -551,25 +552,63 @@
"right": "0" "right": "0"
} }
} }
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "diligent_jstk_system_ila_0_0",
"xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_NUM_MONITOR_SLOTS": {
"value": "2"
},
"C_SLOT": {
"value": "1"
},
"C_SLOT_0_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
},
"C_SLOT_1_INTF_TYPE": {
"value": "xilinx.com:interface:axis_rtl:1.0"
}
},
"interface_ports": {
"SLOT_0_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
},
"SLOT_1_AXIS": {
"mode": "Monitor",
"vlnv": "xilinx.com:interface:axis_rtl:1.0"
}
}
} }
}, },
"interface_nets": { "interface_nets": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": { "jstk_uart_bridge_0_m_axis": {
"interface_ports": [ "interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX", "AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis" "jstk_uart_bridge_0/m_axis"
] ]
}, },
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": { "digilent_jstk2_0_m_axis": {
"interface_ports": [ "interface_ports": [
"digilent_jstk2_0/m_axis", "digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS" "axi4stream_spi_master_0/S_AXIS",
"system_ila_0/SLOT_0_AXIS"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
] ]
}, },
"AXI4Stream_UART_0_UART": { "AXI4Stream_UART_0_UART": {
@@ -583,12 +622,6 @@
"SPI_M_0", "SPI_M_0",
"axi4stream_spi_master_0/SPI_M" "axi4stream_spi_master_0/SPI_M"
] ]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
} }
}, },
"nets": { "nets": {
@@ -620,7 +653,8 @@
"AXI4Stream_UART_0/m00_axis_rx_aclk", "AXI4Stream_UART_0/m00_axis_rx_aclk",
"jstk_uart_bridge_0/aclk", "jstk_uart_bridge_0/aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk", "AXI4Stream_UART_0/s00_axis_tx_aclk",
"digilent_jstk2_0/aclk" "digilent_jstk2_0/aclk",
"system_ila_0/clk"
] ]
}, },
"digilent_jstk2_0_btn_trigger": { "digilent_jstk2_0_btn_trigger": {
@@ -672,7 +706,8 @@
"jstk_uart_bridge_0/aresetn", "jstk_uart_bridge_0/aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn", "AXI4Stream_UART_0/s00_axis_tx_aresetn",
"axi4stream_spi_master_0/aresetn", "axi4stream_spi_master_0/aresetn",
"digilent_jstk2_0/aresetn" "digilent_jstk2_0/aresetn",
"system_ila_0/resetn"
] ]
}, },
"proc_sys_reset_0_peripheral_reset": { "proc_sys_reset_0_peripheral_reset": {

2
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
View File

@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Wed May 14 13:59:17 2025 --Date : Thu May 15 16:34:14 2025
--Host : Davide-Samsung running 64-bit major release (build 9200) --Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd --Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper --Design : diligent_jstk_wrapper

22
LAB3/sim/tb_digilent_jstk2.vhd
View File

@@ -130,23 +130,29 @@ BEGIN
-- Main loop: wait for CMDSETLEDRGB, then send mem bytes for each byte received -- Main loop: wait for CMDSETLEDRGB, then send mem bytes for each byte received
WHILE TRUE LOOP WHILE TRUE LOOP
WAIT UNTIL rising_edge(aclk); WAIT UNTIL rising_edge(aclk);
-- Default: s_axis_tvalid low unless sending
s_axis_tvalid <= '0';
IF m_axis_tvalid = '1' THEN IF m_axis_tvalid = '1' THEN
IF m_axis_tdata = CMDSETLEDRGB THEN IF m_axis_tdata = CMDSETLEDRGB THEN
send_data := TRUE; send_data := TRUE;
mem_idx := 0; mem_idx := 0;
END IF; END IF;
IF send_data THEN IF send_data AND mem_idx <= 4 THEN
IF mem_idx <= 4 THEN -- Present data for one cycle when master is ready
s_axis_tdata <= spi_mem(mem_idx); s_axis_tdata <= spi_mem(mem_idx);
s_axis_tvalid <= '1'; s_axis_tvalid <= '1';
mem_idx := mem_idx + 1; WAIT UNTIL rising_edge(aclk); -- handshake
ELSE s_axis_tvalid <= '0';
mem_idx := mem_idx + 1;
-- Simula il tempo di risposta reale del JSTK2 (1,6 ms per byte)
WAIT FOR 1600 us;
IF mem_idx > 4 THEN
send_data := FALSE; send_data := FALSE;
END IF; END IF;
END IF; END IF;
ELSE
s_axis_tvalid <= '0';
END IF; END IF;
END LOOP; END LOOP;
END PROCESS; END PROCESS;

291
LAB3/src/digilent_jstk2.vhd
View File

@@ -2,192 +2,177 @@ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY digilent_jstk2 IS ENTITY digilent_jstk2 IS
GENERIC ( GENERIC (
DELAY_US : INTEGER := 25; -- Delay (in us) between two packets DELAY_US : INTEGER := 25; -- Delay (in us) between two packets
CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz) CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
SPI_SCLKFREQ : INTEGER := 66_666 -- Frequency of the SPI SCLK clock signal (in Hz) SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
); );
PORT ( PORT (
aclk : IN STD_LOGIC; aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC; aresetn : IN STD_LOGIC;
-- Data going TO the SPI IP-Core (and so, to the JSTK2 module) -- Data going TO the SPI IP-Core (and so, to the JSTK2 module)
m_axis_tvalid : OUT STD_LOGIC; m_axis_tvalid : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tready : IN STD_LOGIC; m_axis_tready : IN STD_LOGIC;
-- Data coming FROM the SPI IP-Core (and so, from the JSTK2 module) -- Data coming FROM the SPI IP-Core (and so, from the JSTK2 module)
-- There is no tready signal, so you must be always ready to accept and use the incoming data, or it will be lost! -- There is no tready signal, so you must be always ready to accept and use the incoming data, or it will be lost!
s_axis_tvalid : IN STD_LOGIC; s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Joystick and button values read from the module -- Joystick and button values read from the module
jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
btn_jstk : OUT STD_LOGIC; btn_jstk : OUT STD_LOGIC;
btn_trigger : OUT STD_LOGIC; btn_trigger : OUT STD_LOGIC;
-- LED color to send to the module -- LED color to send to the module
led_r : IN STD_LOGIC_VECTOR(7 DOWNTO 0); led_r : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
led_g : IN STD_LOGIC_VECTOR(7 DOWNTO 0); led_g : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
led_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0) led_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
); );
END digilent_jstk2; END digilent_jstk2;
ARCHITECTURE Behavioral OF digilent_jstk2 IS ARCHITECTURE Behavioral OF digilent_jstk2 IS
-- Code for the SetLEDRGB command, see the JSTK2 datasheet. -- Code for the SetLEDRGB command, see the JSTK2 datasheet.
CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84"; CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84";
-- Do not forget that you MUST wait a bit between two packets. See the JSTK2 datasheet (and the SPI IP-Core README). -- Do not forget that you MUST wait a bit between two packets. See the JSTK2 datasheet (and the SPI IP-Core README).
------------------------------------------------------------ ------------------------------------------------------------
CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000) - 1; CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000) - 1;
-- State machine states -- State machine states
TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY); TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
TYPE rx_state_type IS (JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS); TYPE rx_state_type IS (IDLE, JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
SIGNAL tx_state : tx_state_type; SIGNAL tx_state : tx_state_type := DELAY;
SIGNAL rx_state : rx_state_type; SIGNAL rx_state : rx_state_type := JSTK_X_LOW;
SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL tx_delay_counter : INTEGER := 0;
SIGNAL tx_delay_counter : INTEGER := 0;
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0'; SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rx_done : STD_LOGIC := '1'; -- Pronto a trasmettere al primo ciclo
BEGIN BEGIN
-- The SPI IP-Core is a slave, so we must set the m_axis_tvalid signal to '1' when we want to send data to it.
WITH tx_state SELECT m_axis_tvalid <=
'0' WHEN DELAY,
'1' WHEN OTHERS;
m_axis_tvalid <= m_axis_tvalid_int; -- TX FSM: invia un nuovo comando solo dopo che la risposta precedente <20> stata ricevuta (rx_done = '1')
TX : PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
tx_state <= DELAY;
m_axis_tdata <= (OTHERS => '0');
tx_delay_counter <= 0;
-- Send the data to the SPI IP-Core ELSE
TX : PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
-- Reset the state machine
tx_state <= DELAY;
m_axis_tvalid_int <= '0'; CASE tx_state IS
m_axis_tdata <= (OTHERS => '0'); WHEN DELAY =>
m_axis_tdata <= (OTHERS => '0');
IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
IF rx_done = '1' THEN
tx_delay_counter <= 0;
tx_state <= SEND_CMD;
END IF;
ELSE
tx_delay_counter <= tx_delay_counter + 1;
END IF;
tx_delay_counter <= 0; WHEN SEND_CMD =>
m_axis_tdata <= CMDSETLEDRGB;
IF m_axis_tready = '1' THEN
tx_state <= SEND_RED;
END IF;
ELSE WHEN SEND_RED =>
-- Clear valid flag when master interface is ready m_axis_tdata <= led_r;
IF m_axis_tready = '1' THEN IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0'; tx_state <= SEND_GREEN;
END IF; END IF;
-- State machine for sending data to the SPI IP-Core WHEN SEND_GREEN =>
CASE tx_state IS m_axis_tdata <= led_g;
IF m_axis_tready = '1' THEN
tx_state <= SEND_BLUE;
END IF;
WHEN DELAY => WHEN SEND_BLUE =>
m_axis_tvalid_int <= '0'; m_axis_tdata <= led_b;
m_axis_tdata <= (OTHERS => '0'); IF m_axis_tready = '1' THEN
tx_state <= SEND_DUMMY;
END IF;
IF tx_delay_counter >= DELAY_CLK_CYCLES THEN WHEN SEND_DUMMY =>
tx_delay_counter <= 0; m_axis_tdata <= (OTHERS => '0');
tx_state <= SEND_CMD; IF m_axis_tready = '1' THEN
ELSE tx_state <= DELAY;
tx_delay_counter <= tx_delay_counter + 1; END IF;
END IF; END CASE;
END IF;
END IF;
END PROCESS TX;
WHEN SEND_CMD => -- RX FSM: riceve 5 byte, aggiorna le uscite e segnala a TX FSM quando la risposta <20> completa
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN RX : PROCESS (aclk)
m_axis_tdata <= CMDSETLEDRGB; BEGIN
m_axis_tvalid_int <= '1'; IF rising_edge(aclk) THEN
tx_state <= SEND_RED;
END IF;
WHEN SEND_RED => IF aresetn = '0' THEN
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tdata <= led_r;
m_axis_tvalid_int <= '1';
tx_state <= SEND_GREEN;
END IF;
WHEN SEND_GREEN => rx_state <= IDLE;
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN rx_cache <= (OTHERS => '0');
m_axis_tdata <= led_g; rx_done <= '1';
m_axis_tvalid_int <= '1';
tx_state <= SEND_BLUE;
END IF;
WHEN SEND_BLUE => ELSE
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tdata <= led_b;
m_axis_tvalid_int <= '1';
tx_state <= SEND_DUMMY;
END IF;
WHEN SEND_DUMMY => CASE rx_state IS
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN WHEN IDLE =>
m_axis_tdata <= (OTHERS => '0'); IF tx_state = SEND_CMD THEN
m_axis_tvalid_int <= '1'; rx_state <= JSTK_X_LOW;
tx_state <= DELAY; rx_done <= '0'; -- In attesa di ricevere la risposta
END IF; END IF;
END CASE; WHEN JSTK_X_LOW =>
IF s_axis_tvalid = '1' THEN
rx_cache <= s_axis_tdata;
rx_state <= JSTK_X_HIGH;
END IF;
END IF; WHEN JSTK_X_HIGH =>
END IF; IF s_axis_tvalid = '1' THEN
jstk_x <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
rx_state <= JSTK_Y_LOW;
END IF;
END PROCESS TX; WHEN JSTK_Y_LOW =>
IF s_axis_tvalid = '1' THEN
rx_cache <= s_axis_tdata;
rx_state <= JSTK_Y_HIGH;
END IF;
-- Receive the data from the SPI IP-Core WHEN JSTK_Y_HIGH =>
RX : PROCESS (aclk) IF s_axis_tvalid = '1' THEN
BEGIN jstk_y <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
IF rising_edge(aclk) THEN rx_state <= BUTTONS;
IF aresetn = '0' THEN END IF;
-- Reset the state machine
rx_state <= JSTK_X_LOW;
-- jstk_x <= (others => '0'); WHEN BUTTONS =>
-- jstk_y <= (others => '0'); IF s_axis_tvalid = '1' THEN
btn_jstk <= '0'; btn_jstk <= s_axis_tdata(0);
btn_trigger <= '0'; btn_trigger <= s_axis_tdata(1);
rx_state <= IDLE;
rx_cache <= (OTHERS => '0'); rx_done <= '1'; -- Risposta completa ricevuta
ELSE END IF;
-- State machine for receiving data from the SPI IP-Core END CASE;
CASE rx_state IS END IF;
END IF;
WHEN JSTK_X_LOW => END PROCESS RX;
IF s_axis_tvalid = '1' THEN
rx_cache(7 DOWNTO 0) <= s_axis_tdata;
rx_state <= JSTK_X_HIGH;
END IF;
WHEN JSTK_X_HIGH =>
IF s_axis_tvalid = '1' THEN
jstk_x(9 DOWNTO 0) <= s_axis_tdata(1 DOWNTO 0) & rx_cache(7 DOWNTO 0);
rx_state <= JSTK_Y_LOW;
END IF;
WHEN JSTK_Y_LOW =>
IF s_axis_tvalid = '1' THEN
rx_cache(7 DOWNTO 0) <= s_axis_tdata;
rx_state <= JSTK_Y_HIGH;
END IF;
WHEN JSTK_Y_HIGH =>
IF s_axis_tvalid = '1' THEN
jstk_y(9 DOWNTO 0) <= s_axis_tdata(1 DOWNTO 0) & rx_cache(7 DOWNTO 0);
rx_state <= BUTTONS;
END IF;
WHEN BUTTONS =>
IF s_axis_tvalid = '1' THEN
btn_jstk <= s_axis_tdata(0);
btn_trigger <= s_axis_tdata(1);
rx_state <= JSTK_X_LOW;
END IF;
END CASE;
END IF;
END IF;
END PROCESS RX;
END ARCHITECTURE; END ARCHITECTURE;

25
LAB3/test/uart_viewer.py
View File

@@ -1,11 +1,24 @@
import serial import serial
import serial.tools.list_ports
import time import time
# CONFIGURAZIONE # CONFIGURAZIONE
PORT = 'COM4' # Cambia con la tua porta: es. 'COM3' su Windows o '/dev/ttyUSB0' su Linux BASYS3_PID = 0x6010
BASYS3_VID = 0x0403
BAUDRATE = 115200 # Imposta la tua velocità BAUDRATE = 115200 # Imposta la tua velocità
CHUNK_SIZE = 4 # 4 byte per riga CHUNK_SIZE = 4 # 4 byte per riga
# Ricerca automatica della porta Basys3
dev = ""
for port in serial.tools.list_ports.comports():
if (port.vid == BASYS3_VID and port.pid == BASYS3_PID):
dev = port.device
if not dev:
raise RuntimeError("Basys 3 Not Found!")
PORT = dev
def receive_mode(ser): def receive_mode(ser):
print("Modalità ricezione. Premi Ctrl+C per uscire.\n") print("Modalità ricezione. Premi Ctrl+C per uscire.\n")
while True: while True:
@@ -41,16 +54,20 @@ def send_mode(ser):
try: try:
mode = "" mode = ""
while mode not in ["r", "s"]: while mode not in ["r", "s", "4"]:
mode = input("Vuoi ricevere (r) o inviare (s) dati? [r/s]: ").strip().lower() mode = input("Vuoi ricevere (r), inviare (s) ? [r/s]: ").strip().lower()
ser = serial.Serial(PORT, BAUDRATE, timeout=1) ser = serial.Serial(PORT, BAUDRATE, timeout=1)
print(f"Aperta porta seriale: {PORT} a {BAUDRATE} baud.\n") print(f"Aperta porta seriale: {PORT} a {BAUDRATE} baud.\n")
if mode == "r": if mode == "r":
receive_mode(ser) receive_mode(ser)
else: elif mode == "s":
send_mode(ser) send_mode(ser)
else:
print("Selezione non valida. Uscita...")
ser.close()
exit(1)
except KeyboardInterrupt: except KeyboardInterrupt:
print("\nChiusura programma...") print("\nChiusura programma...")

276
LAB3/vivado/diligent_jstk/diligent_jstk.xpr
View File

@@ -48,20 +48,20 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/> <Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="29"/> <Option Name="WTXSimLaunchSim" Val="45"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="7"/> <Option Name="WTXSimExportSim" Val="8"/>
<Option Name="WTModelSimExportSim" Val="7"/> <Option Name="WTModelSimExportSim" Val="8"/>
<Option Name="WTQuestaExportSim" Val="7"/> <Option Name="WTQuestaExportSim" Val="8"/>
<Option Name="WTIesExportSim" Val="7"/> <Option Name="WTIesExportSim" Val="8"/>
<Option Name="WTVcsExportSim" Val="7"/> <Option Name="WTVcsExportSim" Val="8"/>
<Option Name="WTRivieraExportSim" Val="7"/> <Option Name="WTRivieraExportSim" Val="8"/>
<Option Name="WTActivehdlExportSim" Val="7"/> <Option Name="WTActivehdlExportSim" Val="8"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@@ -95,6 +95,27 @@
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_clk_wiz_0_1/diligent_jstk_clk_wiz_0_1.xci">
<Proxy FileSetName="diligent_jstk_clk_wiz_0_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_proc_sys_reset_0_0/diligent_jstk_proc_sys_reset_0_0.xci">
<Proxy FileSetName="diligent_jstk_proc_sys_reset_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_AXI4Stream_UART_0_0/diligent_jstk_AXI4Stream_UART_0_0.xci">
<Proxy FileSetName="diligent_jstk_AXI4Stream_UART_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_jstk_uart_bridge_0_0/diligent_jstk_jstk_uart_bridge_0_0.xci">
<Proxy FileSetName="diligent_jstk_jstk_uart_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_axi4stream_spi_master_0_0/diligent_jstk_axi4stream_spi_master_0_0.xci">
<Proxy FileSetName="diligent_jstk_axi4stream_spi_master_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_digilent_jstk2_0_0/diligent_jstk_digilent_jstk2_0_0.xci">
<Proxy FileSetName="diligent_jstk_digilent_jstk2_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_system_ila_0_0/diligent_jstk_system_ila_0_0.xci">
<Proxy FileSetName="diligent_jstk_system_ila_0_0"/>
</CompFileExtendedInfo>
</File> </File>
<File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd"> <File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd">
<FileInfo> <FileInfo>
@@ -143,6 +164,48 @@
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="diligent_jstk_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_proc_sys_reset_0_0" RelGenDir="$PGENDIR/diligent_jstk_proc_sys_reset_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_proc_sys_reset_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_clk_wiz_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_clk_wiz_0_1" RelGenDir="$PGENDIR/diligent_jstk_clk_wiz_0_1">
<Config>
<Option Name="TopModule" Val="diligent_jstk_clk_wiz_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/diligent_jstk_AXI4Stream_UART_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_AXI4Stream_UART_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_jstk_uart_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_jstk_uart_bridge_0_0" RelGenDir="$PGENDIR/diligent_jstk_jstk_uart_bridge_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_jstk_uart_bridge_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_axi4stream_spi_master_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_axi4stream_spi_master_0_0" RelGenDir="$PGENDIR/diligent_jstk_axi4stream_spi_master_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_axi4stream_spi_master_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_digilent_jstk2_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_digilent_jstk2_0_0" RelGenDir="$PGENDIR/diligent_jstk_digilent_jstk2_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_digilent_jstk2_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_system_ila_0_0" RelGenDir="$PGENDIR/diligent_jstk_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets> </FileSets>
<Simulators> <Simulators>
<Simulator Name="XSim"> <Simulator Name="XSim">
@@ -173,6 +236,80 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_clk_wiz_0_1_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_clk_wiz_0_1" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_clk_wiz_0_1_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_1_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_jstk_uart_bridge_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_axi4stream_spi_master_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_digilent_jstk2_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_digilent_jstk2_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_digilent_jstk2_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_digilent_jstk2_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_digilent_jstk2_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_system_ila_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
@@ -191,6 +328,129 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_clk_wiz_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_clk_wiz_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_1_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_digilent_jstk2_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_digilent_jstk2_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_digilent_jstk2_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_digilent_jstk2_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs> </Runs>
<Board> <Board>
<Jumpers/> <Jumpers/>