Refactor RGB to Grayscale conversion: update divider component and add testbench
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102
LAB2/sim/tb_rgb2gray.vhd
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102
LAB2/sim/tb_rgb2gray.vhd
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-- Testbench for rgb2gray
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY rgb2gray_tb IS
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END rgb2gray_tb;
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ARCHITECTURE Behavioral OF rgb2gray_tb IS
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-- Component Declaration
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COMPONENT rgb2gray
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PORT (
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clk : IN STD_LOGIC;
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resetn : IN STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC
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);
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END COMPONENT;
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-- Signals
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL resetn : STD_LOGIC := '0';
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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-- Clock generation
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CONSTANT clk_period : TIME := 10 ns;
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BEGIN
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m_axis_tready<='1';
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clk <= not clk AFTER clk_period / 2; -- Clock generation
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-- Instantiate the Device Under Test (DUT)
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DUT: rgb2gray
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PORT MAP (
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clk => clk,
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resetn => resetn,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tready => s_axis_tready,
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s_axis_tlast => s_axis_tlast
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);
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-- Stimulus process
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stimulus_process : PROCESS
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VARIABLE pixel_value : INTEGER := 1; -- Variable to increment pixel values
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BEGIN
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wait for 10 ns;
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resetn<='1';
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s_axis_tvalid <= '1';
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-- Send multiple RGB pixels with incrementing values
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FOR i IN 0 TO 10 LOOP -- Send 10 pixels
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-- R component
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- G component
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pixel_value := pixel_value + 5;
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- B component
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pixel_value := pixel_value + 1;
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- Reset last signal
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pixel_value := pixel_value + 1;
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END LOOP;
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-- Deassert valid signal
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s_axis_tlast <= '1'; -- Indicate end of pixel
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s_axis_tvalid <= '0';
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WAIT;
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END PROCESS;
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END Behavioral;
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