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Refactor RGB to Grayscale conversion: update divider component and add testbench

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This commit is contained in:
Davide Cavagnola
2025-04-11 13:00:46 +02:00
parent 0d805b93b6
commit c712b160cc
4 changed files with 336 additions and 29 deletions
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16
LAB2/src/divider_by_3.vhd
View File

@@ -10,10 +10,8 @@ ENTITY divider_by_3 IS
BIT_DEPTH : INTEGER := 8
);
PORT (
R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0)
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
gray : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
);
END divider_by_3;
@@ -26,7 +24,7 @@ ARCHITECTURE Behavioral OF divider_by_3 IS
-- Signals to hold the sum of the RGB channels and the intermediate results
SIGNAL rgb_sum_extended : UNSIGNED(BIT_DEPTH + 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL scaled_result : UNSIGNED(RESULT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL scaled_result : UNSIGNED(RESULT_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL grayscale_value : UNSIGNED(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
@@ -39,15 +37,15 @@ BEGIN
-- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector.
-- Calculate the sum of the RGB channels
rgb_sum_extended <= UNSIGNED(R) + UNSIGNED(G) + UNSIGNED(B) + TO_UNSIGNED(2, BIT_DEPTH + 2);
rgb_sum_extended <= dividend + TO_UNSIGNED(2, BIT_DEPTH + 2);
-- Multiply the sum by the precomputed multiplier
scaled_result <= rgb_sum_extended * TO_UNSIGNED(DIVISION_MULTIPLIER, RESULT_WIDTH);
scaled_result <= rgb_sum_extended * TO_UNSIGNED(DIVISION_MULTIPLIER, BIT_DEPTH + 1);
-- Extract the grayscale value from the scaled result by right-shifting
grayscale_value <= scaled_result(RESULT_WIDTH - 1 DOWNTO RESULT_WIDTH - BIT_DEPTH - 1);
grayscale_value <= scaled_result(RESULT_WIDTH - 1 DOWNTO RESULT_WIDTH - BIT_DEPTH);
-- Assign the grayscale value to the output
grey <= STD_LOGIC_VECTOR(grayscale_value);
gray <= grayscale_value;
END Behavioral;

36
LAB2/src/rgb2gray.vhd
View File

@@ -33,17 +33,16 @@ ARCHITECTURE Behavioral OF rgb2gray IS
BIT_DEPTH : INTEGER := 8
);
PORT (
R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0));
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
gray : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0));
END COMPONENT divider_by_3;
TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B);
SIGNAL state : state_type := WAIT_R;
SIGNAL r_val, g_val, b_val : unsigned(7 DOWNTO 0);
SIGNAL gray : unsigned(7 DOWNTO 0);
SIGNAL r_val, g_val : unsigned(7 DOWNTO 0);
SIGNAL sum : unsigned(9 DOWNTO 0);
SIGNAL gray : UNSIGNED(7 DOWNTO 0);
BEGIN
@@ -52,10 +51,8 @@ BEGIN
BIT_DEPTH => 8
)
PORT MAP(
R => STD_LOGIC_VECTOR(r_val),
G => STD_LOGIC_VECTOR(g_val),
B => STD_LOGIC_VECTOR(b_val),
grey => STD_LOGIC_VECTOR(gray)
dividend => sum,
gray => gray
);
PROCESS (clk)
@@ -70,14 +67,18 @@ BEGIN
m_axis_tdata <= (OTHERS => '0');
r_val <= (OTHERS => '0');
g_val <= (OTHERS => '0');
b_val <= (OTHERS => '0');
gray <= (OTHERS => '0');
sum <= (OTHERS => '0');
ELSE
-- Default control signals
s_axis_tready <= '1';
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
-- If downstream is ready, send the grayscale pixel
IF m_axis_tready = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(gray);
m_axis_tlast <= s_axis_tlast;
END IF;
CASE state IS
WHEN WAIT_R =>
IF s_axis_tvalid = '1' THEN
@@ -93,16 +94,11 @@ BEGIN
WHEN WAIT_B =>
IF s_axis_tvalid = '1' THEN
b_val <= unsigned(s_axis_tdata);
END IF;
-- If downstream is ready, send the grayscale pixel
IF m_axis_tready = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(gray);
sum <= ('0' & '0' & r_val) + ('0' & '0' & g_val) + ('0' & '0' & unsigned(s_axis_tdata));
m_axis_tvalid <= '1';
m_axis_tlast <= s_axis_tlast;
state <= WAIT_R;
END IF;
END CASE;
END IF;
END IF;