Refactor RGB to Grayscale conversion: update divider component and add testbench
This commit is contained in:
102
LAB2/sim/tb_rgb2gray.vhd
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102
LAB2/sim/tb_rgb2gray.vhd
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@@ -0,0 +1,102 @@
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-- Testbench for rgb2gray
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY rgb2gray_tb IS
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END rgb2gray_tb;
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ARCHITECTURE Behavioral OF rgb2gray_tb IS
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-- Component Declaration
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COMPONENT rgb2gray
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PORT (
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clk : IN STD_LOGIC;
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resetn : IN STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC
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);
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END COMPONENT;
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-- Signals
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL resetn : STD_LOGIC := '0';
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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-- Clock generation
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CONSTANT clk_period : TIME := 10 ns;
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BEGIN
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m_axis_tready<='1';
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clk <= not clk AFTER clk_period / 2; -- Clock generation
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-- Instantiate the Device Under Test (DUT)
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DUT: rgb2gray
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PORT MAP (
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clk => clk,
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resetn => resetn,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tready => s_axis_tready,
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s_axis_tlast => s_axis_tlast
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);
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-- Stimulus process
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stimulus_process : PROCESS
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VARIABLE pixel_value : INTEGER := 1; -- Variable to increment pixel values
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BEGIN
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wait for 10 ns;
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resetn<='1';
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s_axis_tvalid <= '1';
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-- Send multiple RGB pixels with incrementing values
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FOR i IN 0 TO 10 LOOP -- Send 10 pixels
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-- R component
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- G component
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pixel_value := pixel_value + 5;
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- B component
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pixel_value := pixel_value + 1;
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
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WAIT FOR clk_period;
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-- Reset last signal
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pixel_value := pixel_value + 1;
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END LOOP;
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-- Deassert valid signal
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s_axis_tlast <= '1'; -- Indicate end of pixel
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s_axis_tvalid <= '0';
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WAIT;
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END PROCESS;
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END Behavioral;
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@@ -10,10 +10,8 @@ ENTITY divider_by_3 IS
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BIT_DEPTH : INTEGER := 8
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BIT_DEPTH : INTEGER := 8
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);
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);
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PORT (
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PORT (
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R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
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G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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gray : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
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B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0)
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);
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);
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END divider_by_3;
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END divider_by_3;
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@@ -26,7 +24,7 @@ ARCHITECTURE Behavioral OF divider_by_3 IS
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-- Signals to hold the sum of the RGB channels and the intermediate results
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-- Signals to hold the sum of the RGB channels and the intermediate results
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SIGNAL rgb_sum_extended : UNSIGNED(BIT_DEPTH + 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL rgb_sum_extended : UNSIGNED(BIT_DEPTH + 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL scaled_result : UNSIGNED(RESULT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL scaled_result : UNSIGNED(RESULT_WIDTH DOWNTO 0) := (OTHERS => '0');
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SIGNAL grayscale_value : UNSIGNED(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL grayscale_value : UNSIGNED(BIT_DEPTH - 1 DOWNTO 0) := (OTHERS => '0');
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BEGIN
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BEGIN
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@@ -39,15 +37,15 @@ BEGIN
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-- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector.
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-- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector.
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-- Calculate the sum of the RGB channels
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-- Calculate the sum of the RGB channels
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rgb_sum_extended <= UNSIGNED(R) + UNSIGNED(G) + UNSIGNED(B) + TO_UNSIGNED(2, BIT_DEPTH + 2);
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rgb_sum_extended <= dividend + TO_UNSIGNED(2, BIT_DEPTH + 2);
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-- Multiply the sum by the precomputed multiplier
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-- Multiply the sum by the precomputed multiplier
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scaled_result <= rgb_sum_extended * TO_UNSIGNED(DIVISION_MULTIPLIER, RESULT_WIDTH);
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scaled_result <= rgb_sum_extended * TO_UNSIGNED(DIVISION_MULTIPLIER, BIT_DEPTH + 1);
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-- Extract the grayscale value from the scaled result by right-shifting
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-- Extract the grayscale value from the scaled result by right-shifting
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grayscale_value <= scaled_result(RESULT_WIDTH - 1 DOWNTO RESULT_WIDTH - BIT_DEPTH - 1);
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grayscale_value <= scaled_result(RESULT_WIDTH - 1 DOWNTO RESULT_WIDTH - BIT_DEPTH);
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-- Assign the grayscale value to the output
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-- Assign the grayscale value to the output
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grey <= STD_LOGIC_VECTOR(grayscale_value);
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gray <= grayscale_value;
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END Behavioral;
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END Behavioral;
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@@ -33,17 +33,16 @@ ARCHITECTURE Behavioral OF rgb2gray IS
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BIT_DEPTH : INTEGER := 8
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BIT_DEPTH : INTEGER := 8
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);
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);
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PORT (
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PORT (
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R : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
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G : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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gray : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0));
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B : IN STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0);
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grey : OUT STD_LOGIC_VECTOR(BIT_DEPTH - 1 DOWNTO 0));
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END COMPONENT divider_by_3;
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END COMPONENT divider_by_3;
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TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B);
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TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B);
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SIGNAL state : state_type := WAIT_R;
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SIGNAL state : state_type := WAIT_R;
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SIGNAL r_val, g_val, b_val : unsigned(7 DOWNTO 0);
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SIGNAL r_val, g_val : unsigned(7 DOWNTO 0);
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SIGNAL gray : unsigned(7 DOWNTO 0);
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SIGNAL sum : unsigned(9 DOWNTO 0);
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SIGNAL gray : UNSIGNED(7 DOWNTO 0);
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BEGIN
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BEGIN
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@@ -52,10 +51,8 @@ BEGIN
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BIT_DEPTH => 8
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BIT_DEPTH => 8
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)
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)
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PORT MAP(
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PORT MAP(
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R => STD_LOGIC_VECTOR(r_val),
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dividend => sum,
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G => STD_LOGIC_VECTOR(g_val),
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gray => gray
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B => STD_LOGIC_VECTOR(b_val),
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grey => STD_LOGIC_VECTOR(gray)
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);
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);
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PROCESS (clk)
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PROCESS (clk)
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@@ -70,14 +67,18 @@ BEGIN
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m_axis_tdata <= (OTHERS => '0');
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m_axis_tdata <= (OTHERS => '0');
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r_val <= (OTHERS => '0');
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r_val <= (OTHERS => '0');
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g_val <= (OTHERS => '0');
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g_val <= (OTHERS => '0');
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b_val <= (OTHERS => '0');
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sum <= (OTHERS => '0');
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gray <= (OTHERS => '0');
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ELSE
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ELSE
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-- Default control signals
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-- Default control signals
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s_axis_tready <= '1';
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s_axis_tready <= '1';
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m_axis_tvalid <= '0';
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m_axis_tlast <= '0';
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m_axis_tlast <= '0';
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-- If downstream is ready, send the grayscale pixel
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IF m_axis_tready = '1' THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(gray);
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m_axis_tlast <= s_axis_tlast;
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END IF;
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CASE state IS
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CASE state IS
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WHEN WAIT_R =>
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WHEN WAIT_R =>
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IF s_axis_tvalid = '1' THEN
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IF s_axis_tvalid = '1' THEN
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@@ -93,16 +94,11 @@ BEGIN
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WHEN WAIT_B =>
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WHEN WAIT_B =>
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IF s_axis_tvalid = '1' THEN
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IF s_axis_tvalid = '1' THEN
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b_val <= unsigned(s_axis_tdata);
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sum <= ('0' & '0' & r_val) + ('0' & '0' & g_val) + ('0' & '0' & unsigned(s_axis_tdata));
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END IF;
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-- If downstream is ready, send the grayscale pixel
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IF m_axis_tready = '1' THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(gray);
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m_axis_tvalid <= '1';
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m_axis_tvalid <= '1';
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m_axis_tlast <= s_axis_tlast;
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state <= WAIT_R;
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state <= WAIT_R;
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END IF;
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END IF;
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END CASE;
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END CASE;
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END IF;
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END IF;
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END IF;
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END IF;
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211
LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr
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211
LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="2e783875aa14478a86d117fd6ef68faf"/>
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<Option Name="Part" Val="xc7a35tcpg236-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirIES" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirIES" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="TargetLanguage" Val="VHDL"/>
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<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
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<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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||||||
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<Option Name="ProjectType" Val="Default"/>
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||||||
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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||||||
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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||||||
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<Option Name="IPCachePermission" Val="read"/>
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||||||
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<Option Name="IPCachePermission" Val="write"/>
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||||||
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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||||||
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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||||||
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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||||||
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||||
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<Option Name="EnableBDX" Val="FALSE"/>
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||||||
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<Option Name="DSABoardId" Val="basys3"/>
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||||||
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<Option Name="WTXSimLaunchSim" Val="50"/>
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||||||
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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||||||
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||||
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<Option Name="WTIesLaunchSim" Val="0"/>
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||||||
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<Option Name="WTVcsLaunchSim" Val="0"/>
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||||||
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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||||||
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||||
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<Option Name="WTXSimExportSim" Val="0"/>
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||||||
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<Option Name="WTModelSimExportSim" Val="0"/>
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||||||
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<Option Name="WTQuestaExportSim" Val="0"/>
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||||||
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<Option Name="WTIesExportSim" Val="0"/>
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||||||
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<Option Name="WTVcsExportSim" Val="0"/>
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||||||
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<Option Name="WTRivieraExportSim" Val="0"/>
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||||||
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<Option Name="WTActivehdlExportSim" Val="0"/>
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||||||
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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||||||
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<Option Name="XSimRadix" Val="hex"/>
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||||||
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<Option Name="XSimTimeUnit" Val="ns"/>
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||||||
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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||||||
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<Option Name="XSimTraceLimit" Val="65536"/>
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||||||
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<Option Name="SimTypes" Val="rtl"/>
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||||||
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<Option Name="SimTypes" Val="bfm"/>
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||||||
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<Option Name="SimTypes" Val="tlm"/>
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||||||
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<Option Name="SimTypes" Val="tlm_dpi"/>
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||||||
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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||||||
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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||||||
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</Configuration>
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||||||
|
<FileSets Version="1" Minor="31">
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||||||
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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||||||
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<File Path="$PPRDIR/../../src/divider_by_3.vhd">
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<FileInfo>
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||||||
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<Attr Name="UsedIn" Val="synthesis"/>
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||||||
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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||||||
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<File Path="$PPRDIR/../../src/rgb2gray.vhd">
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<FileInfo>
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||||||
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<Attr Name="UsedIn" Val="synthesis"/>
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||||||
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<Attr Name="UsedIn" Val="simulation"/>
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||||||
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</FileInfo>
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||||||
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</File>
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||||||
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<Config>
|
||||||
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<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="rgb2gray"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../../sim/tb_rgb2gray.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="rgb2gray_tb"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="15">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board>
|
||||||
|
<Jumpers/>
|
||||||
|
</Board>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user