diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bd b/LAB3/design/diligent_jstk/diligent_jstk.bd
index 872682e..d267b4c 100644
--- a/LAB3/design/diligent_jstk/diligent_jstk.bd
+++ b/LAB3/design/diligent_jstk/diligent_jstk.bd
@@ -591,31 +591,24 @@
}
},
"interface_nets": {
- "AXI4Stream_UART_0_M00_AXIS_RX": {
- "interface_ports": [
- "AXI4Stream_UART_0/M00_AXIS_RX",
- "jstk_uart_bridge_0/s_axis"
- ]
- },
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
+ "AXI4Stream_UART_0_M00_AXIS_RX": {
+ "interface_ports": [
+ "AXI4Stream_UART_0/M00_AXIS_RX",
+ "jstk_uart_bridge_0/s_axis"
+ ]
+ },
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
- "digilent_jstk2_0_m_axis": {
- "interface_ports": [
- "digilent_jstk2_0/m_axis",
- "axi4stream_spi_master_0/S_AXIS",
- "system_ila_0/SLOT_0_AXIS"
- ]
- },
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
@@ -628,6 +621,13 @@
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
+ },
+ "digilent_jstk2_0_m_axis": {
+ "interface_ports": [
+ "digilent_jstk2_0/m_axis",
+ "axi4stream_spi_master_0/S_AXIS",
+ "system_ila_0/SLOT_0_AXIS"
+ ]
}
},
"nets": {
diff --git a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
index ed436c0..7ff2210 100644
--- a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
+++ b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date : Sat May 17 13:12:32 2025
+--Date : Sat May 17 14:20:44 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
diff --git a/LAB3/src/digilent_jstk2.vhd b/LAB3/src/digilent_jstk2.vhd
index a89d8c4..1131ce3 100644
--- a/LAB3/src/digilent_jstk2.vhd
+++ b/LAB3/src/digilent_jstk2.vhd
@@ -81,7 +81,6 @@ BEGIN
IF aresetn = '0' THEN
tx_state <= DELAY;
- m_axis_tdata <= (OTHERS => '0');
tx_delay_counter <= 0;
ELSE
diff --git a/LAB3/test/uart_viewer.py b/LAB3/test/uart_viewer.py
index 70cbbb7..da06e82 100644
--- a/LAB3/test/uart_viewer.py
+++ b/LAB3/test/uart_viewer.py
@@ -39,17 +39,21 @@ def receive_graph_mode(ser):
while True:
if ser.in_waiting >= CHUNK_SIZE:
data = ser.read(CHUNK_SIZE)
- if len(data) >= 2:
+ if len(data) >= 4:
x = data[1]
y = data[2]
- q.put((x, y))
+ flags = data[3]
+ q.put((x, y, flags))
reader_thread = threading.Thread(target=serial_reader, daemon=True)
reader_thread.start()
latest_point = [64, 64] # Punto iniziale al centro del grafico
+ latest_color = 'blue'
+ latest_size = 100
+
fig, ax = plt.subplots()
- sc = ax.scatter([latest_point[0]], [latest_point[1]])
+ sc = ax.scatter([latest_point[0]], [latest_point[1]], c=[latest_color], s=[latest_size])
ax.set_xlim(0, 127)
ax.set_ylim(0, 127)
ax.set_xlabel("X")
@@ -57,14 +61,27 @@ def receive_graph_mode(ser):
ax.set_title("Coordinate in tempo reale")
def update(frame):
+ nonlocal latest_point, latest_color, latest_size
while not q.empty():
- x, y = q.get()
+ x, y, flags = q.get()
latest_point[0] = x
latest_point[1] = y
+ # Bit 0: red if set, else blue
+ if flags & 0b00000001:
+ latest_color = 'red'
+ else:
+ latest_color = 'blue'
+ # Bit 1: bigger if set
+ if flags & 0b00000010:
+ latest_size = 300
+ else:
+ latest_size = 100
sc.set_offsets([latest_point])
+ sc.set_color([latest_color])
+ sc.set_sizes([latest_size])
return sc,
- ani = animation.FuncAnimation(fig, update, interval=30, blit=True)
+ ani = animation.FuncAnimation(fig, update, interval=10, blit=True, cache_frame_data=False)
plt.show()
def send_mode(ser):
diff --git a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr
index f0bdb2e..e8c8d8d 100644
--- a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr
+++ b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr
@@ -95,6 +95,27 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -143,6 +164,48 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -173,6 +236,90 @@
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
+
+
+
+ Vivado Synthesis Defaults
+
+
+
+
+
+
+
+
@@ -191,6 +338,139 @@
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Default settings for Implementation.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+