From d156d1c9441bf5c44ca87a967b82597268957587 Mon Sep 17 00:00:00 2001 From: Davide Date: Fri, 30 May 2025 14:14:25 +0200 Subject: [PATCH] Refactor project structure and update dependencies - Updated .gitignore to exclude virtual environment and additional test files. - Modified diligent_jstk.bd to reorganize interface nets for clarity. - Adjusted diligent_jstk.bda to correct node attributes and edges. - Revised diligent_jstk_wrapper.vhd to ensure proper port declarations. - Enhanced uart_viewer.py for improved image handling and serial connection checks. - Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations. - Added requirements.txt to specify project dependencies for Python packages. --- .gitignore | 9 +- LAB3/design/diligent_jstk/diligent_jstk.bd | 26 +- LAB3/design/diligent_jstk/diligent_jstk.bda | 22 +- .../hdl/diligent_jstk_wrapper.vhd | 10 +- LAB3/test/uart_viewer.py | 7 +- LAB3/vivado/diligent_jstk/diligent_jstk.xpr | 222 +++++++++++------- LAB3/vivado/lab3/lab3.xpr | 6 +- requirements.txt | 6 + 8 files changed, 189 insertions(+), 119 deletions(-) create mode 100644 requirements.txt diff --git a/.gitignore b/.gitignore index 299f53b..58ea3db 100644 --- a/.gitignore +++ b/.gitignore @@ -45,7 +45,6 @@ *.bxml *.zip - # Vivado project directories *.sim/ *.cache/ @@ -65,6 +64,8 @@ vivado_pid*.str vivado*.backup.jou vivado*.backup.log +# Directories to ignore +.venv # SDK workspace .sdk/ @@ -79,4 +80,8 @@ vivado*.backup.log **/design/**/*.xdc # Other files -**/test/*.zip \ No newline at end of file +**/test/*.zip +**/test/*.exe +**/test/*.spec +**/test/dist/ +**/test/build/ \ No newline at end of file diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bd b/LAB3/design/diligent_jstk/diligent_jstk.bd index d4628ee..1570bb4 100644 --- a/LAB3/design/diligent_jstk/diligent_jstk.bd +++ b/LAB3/design/diligent_jstk/diligent_jstk.bd @@ -591,13 +591,6 @@ } }, "interface_nets": { - "axi4stream_spi_master_0_M_AXIS": { - "interface_ports": [ - "axi4stream_spi_master_0/M_AXIS", - "digilent_jstk2_0/s_axis", - "system_ila_0/SLOT_1_AXIS" - ] - }, "AXI4Stream_UART_0_M00_AXIS_RX": { "interface_ports": [ "AXI4Stream_UART_0/M00_AXIS_RX", @@ -610,10 +603,17 @@ "axi4stream_spi_master_0/SPI_M" ] }, - "AXI4Stream_UART_0_UART": { + "axi4stream_spi_master_0_M_AXIS": { "interface_ports": [ - "usb_uart", - "AXI4Stream_UART_0/UART" + "axi4stream_spi_master_0/M_AXIS", + "digilent_jstk2_0/s_axis", + "system_ila_0/SLOT_1_AXIS" + ] + }, + "jstk_uart_bridge_0_m_axis": { + "interface_ports": [ + "AXI4Stream_UART_0/S00_AXIS_TX", + "jstk_uart_bridge_0/m_axis" ] }, "digilent_jstk2_0_m_axis": { @@ -623,10 +623,10 @@ "system_ila_0/SLOT_0_AXIS" ] }, - "jstk_uart_bridge_0_m_axis": { + "AXI4Stream_UART_0_UART": { "interface_ports": [ - "AXI4Stream_UART_0/S00_AXIS_TX", - "jstk_uart_bridge_0/m_axis" + "usb_uart", + "AXI4Stream_UART_0/UART" ] } }, diff --git a/LAB3/design/diligent_jstk/diligent_jstk.bda b/LAB3/design/diligent_jstk/diligent_jstk.bda index 1612b92..aafae03 100644 --- a/LAB3/design/diligent_jstk/diligent_jstk.bda +++ b/LAB3/design/diligent_jstk/diligent_jstk.bda @@ -21,22 +21,22 @@ - diligent_jstk - BC - - - active - 2 - PM - - 2 diligent_jstk VR - + + diligent_jstk + BC + + + active + 2 + PM + + - + diff --git a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd index 39455a0..9d1328b 100644 --- a/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd +++ b/LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd @@ -1,8 +1,8 @@ --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 ---Date : Mon May 19 09:11:39 2025 ---Host : Davide-Samsung running 64-bit major release (build 9200) +--Date : Fri May 30 13:56:20 2025 +--Host : DavideASUS running 64-bit major release (build 9200) --Command : generate_target diligent_jstk_wrapper.bd --Design : diligent_jstk_wrapper --Purpose : IP block netlist @@ -29,8 +29,6 @@ architecture STRUCTURE of diligent_jstk_wrapper is port ( reset : in STD_LOGIC; sys_clock : in STD_LOGIC; - usb_uart_txd : out STD_LOGIC; - usb_uart_rxd : in STD_LOGIC; SPI_M_0_sck_t : out STD_LOGIC; SPI_M_0_io1_o : out STD_LOGIC; SPI_M_0_ss_t : out STD_LOGIC; @@ -42,7 +40,9 @@ architecture STRUCTURE of diligent_jstk_wrapper is SPI_M_0_sck_o : out STD_LOGIC; SPI_M_0_ss_i : in STD_LOGIC; SPI_M_0_io1_i : in STD_LOGIC; - SPI_M_0_io0_i : in STD_LOGIC + SPI_M_0_io0_i : in STD_LOGIC; + usb_uart_txd : out STD_LOGIC; + usb_uart_rxd : in STD_LOGIC ); end component diligent_jstk; component IOBUF is diff --git a/LAB3/test/uart_viewer.py b/LAB3/test/uart_viewer.py index 59f0993..296882a 100644 --- a/LAB3/test/uart_viewer.py +++ b/LAB3/test/uart_viewer.py @@ -63,11 +63,11 @@ def receive_graph_mode(ser): # Load PNG directly png_path = r'LAB3\test\Color_circle_(RGB).png' img = Image.open(png_path).convert('RGB') - img = img.resize((127, 127), Image.LANCZOS) # Ensure image is 127x127 + img = img.resize((127, 127), Image.Resampling.LANCZOS) # Ensure image is 127x127 img_np = np.array(img) # Show the image as background - ax.imshow(img, extent=[0, 127, 0, 127], aspect='auto', zorder=0) + ax.imshow(img, extent=(0, 127, 0, 127), aspect='auto', zorder=0) sc = ax.scatter([point[0]], [point[1]], s=[size], zorder=1) ax.set_xlim(0, 127) @@ -146,6 +146,7 @@ def send_mode(ser): print("\nChiusura modalità invio...") break +ser = None try: mode = "" while mode not in ["r", "s", "g"]: @@ -170,5 +171,5 @@ except KeyboardInterrupt: except serial.SerialException as e: print(f"Errore nella connessione seriale: {e}") finally: - if 'ser' in locals() and ser.is_open: + if ser is not None and ser.is_open: ser.close() diff --git a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr index 6dbb0ee..b3d8a31 100644 --- a/LAB3/vivado/diligent_jstk/diligent_jstk.xpr +++ b/LAB3/vivado/diligent_jstk/diligent_jstk.xpr @@ -77,29 +77,48 @@ - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -145,9 +164,9 @@ - + - @@ -163,27 +182,27 @@ - - - - - + - - + - + + + + @@ -207,79 +226,101 @@ - + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + - + + Vivado Synthesis Defaults + + - + @@ -292,13 +333,16 @@ + - + - + + Default settings for Implementation. + @@ -315,7 +359,9 @@ - + + Default settings for Implementation. + @@ -332,24 +378,9 @@ - - - - - - - - - - - - - - - - - - + + Default settings for Implementation. + @@ -366,7 +397,47 @@ - + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + @@ -383,24 +454,9 @@ - - - - - - - - - - - - - - - - - - + + Default settings for Implementation. + diff --git a/LAB3/vivado/lab3/lab3.xpr b/LAB3/vivado/lab3/lab3.xpr index d278d19..efa626e 100644 --- a/LAB3/vivado/lab3/lab3.xpr +++ b/LAB3/vivado/lab3/lab3.xpr @@ -247,16 +247,17 @@ - + + - + @@ -269,6 +270,7 @@ + diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000..ae328dd --- /dev/null +++ b/requirements.txt @@ -0,0 +1,6 @@ +pyserial +matplotlib +pillow +numpy +tqdm +scipy \ No newline at end of file