diff --git a/LAB3/sim/tb_volume_multiplier.vhd b/LAB3/sim/tb_volume_multiplier.vhd index ccb4e85..b91b495 100644 --- a/LAB3/sim/tb_volume_multiplier.vhd +++ b/LAB3/sim/tb_volume_multiplier.vhd @@ -115,7 +115,7 @@ BEGIN WAIT UNTIL rising_edge(aclk); -- Set volume to mid (no gain/loss) - volume <= volume_mem(0); + volume <= volume_mem(7); WAIT UNTIL rising_edge(aclk); -- Send all samples diff --git a/LAB3/src/balance_controller.vhd b/LAB3/src/balance_controller.vhd index d7e05e5..c1f0d2b 100644 --- a/LAB3/src/balance_controller.vhd +++ b/LAB3/src/balance_controller.vhd @@ -40,9 +40,7 @@ ARCHITECTURE Behavioral OF balance_controller IS BEGIN -- Assigning the output signals m_axis_tvalid <= m_axis_tvalid_int; - s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; -- Chiedere e in caso togliere 'AND aresetn' - - + s_axis_tready <= m_axis_tready OR NOT m_axis_tvalid_int; -- Balance to exp process to avoid changing the balance value when multiplying it for the sample data BALANCE_CALC : PROCESS (aclk) @@ -56,13 +54,13 @@ BEGIN ELSE -- Balance left and right channels - IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN + IF to_integer(unsigned(balance)) > (BAL_MID + DEAD_ZONE) THEN left_channel <= to_integer((unsigned(balance) - to_unsigned(BAL_MID + DEAD_ZONE, balance'length)) SRL BALANCE_STEP_2) + 1; -- +1 due to shift approximation defect ELSE left_channel <= 0; END IF; - IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN + IF to_integer(unsigned(balance)) < (BAL_MID - DEAD_ZONE) THEN right_channel <= to_integer((to_unsigned(BAL_MID - DEAD_ZONE, balance'length) - unsigned(balance)) SRL BALANCE_STEP_2) + 1; ELSE right_channel <= 0; @@ -85,9 +83,6 @@ BEGIN m_axis_tlast <= '0'; ELSE - -- Default output signals - m_axis_tlast <= '0'; - -- Clear valid flag when master interface is ready IF m_axis_tready = '1' THEN m_axis_tvalid_int <= '0'; diff --git a/LAB3/src/effect_selector.vhd b/LAB3/src/effect_selector.vhd index ff97a30..2d7025e 100644 --- a/LAB3/src/effect_selector.vhd +++ b/LAB3/src/effect_selector.vhd @@ -35,14 +35,14 @@ BEGIN ELSE balance <= jstck_x; - IF effect = '0' THEN + IF effect = '1' THEN + -- LFO control + lfo_period <= jstck_y; + + ELSE -- volume/balance control volume <= jstck_y; lfo_period <= (OTHERS => '0'); - - ELSE - -- LFO control - lfo_period <= jstck_y; END IF; diff --git a/LAB3/src/volume_multiplier.vhd b/LAB3/src/volume_multiplier.vhd index bb089b3..dd4f041 100644 --- a/LAB3/src/volume_multiplier.vhd +++ b/LAB3/src/volume_multiplier.vhd @@ -76,9 +76,6 @@ BEGIN m_axis_tlast <= '0'; ELSE - -- Default output signals - m_axis_tlast <= '0'; - -- Clear valid flag when master interface is ready IF m_axis_tready = '1' THEN m_axis_tvalid_int <= '0'; @@ -90,10 +87,10 @@ BEGIN -- Joystick datasheet: (y-axis) a value of 0 when it is tilted all the way down -- and a value of 1023 when it is tilted all the way up IF volume_exp_mult >= 0 THEN - m_axis_tdata <= STD_LOGIC_VECTOR(resize(shift_left(signed(s_axis_tdata), volume_exp_mult), m_axis_tdata'LENGTH)); + m_axis_tdata <= STD_LOGIC_VECTOR(shift_left(resize(signed(s_axis_tdata), m_axis_tdata'LENGTH), volume_exp_mult)); ELSE - m_axis_tdata <= STD_LOGIC_VECTOR(resize(shift_right(signed(s_axis_tdata), - volume_exp_mult), m_axis_tdata'LENGTH)); + m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(resize(signed(s_axis_tdata), m_axis_tdata'LENGTH), - volume_exp_mult)); END IF; diff --git a/LAB3/src/volume_saturator.vhd b/LAB3/src/volume_saturator.vhd index 9a9ab01..10549d4 100644 --- a/LAB3/src/volume_saturator.vhd +++ b/LAB3/src/volume_saturator.vhd @@ -28,12 +28,15 @@ END volume_saturator; ARCHITECTURE Behavioral OF volume_saturator IS + CONSTANT HIGHER_BOUND_VEC : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := STD_LOGIC_VECTOR(to_signed(HIGHER_BOUND, TDATA_WIDTH)); + CONSTANT LOWER_BOUND_VEC : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := STD_LOGIC_VECTOR(to_signed(LOWER_BOUND, TDATA_WIDTH)); + SIGNAL m_axis_tvalid_int : STD_LOGIC; BEGIN -- Output assignments m_axis_tvalid <= m_axis_tvalid_int; - s_axis_tready <= m_axis_tready AND aresetn; + s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; PROCESS (aclk) BEGIN @@ -43,9 +46,8 @@ BEGIN IF aresetn = '0' THEN m_axis_tvalid_int <= '0'; m_axis_tlast <= '0'; - m_axis_tdata <= (OTHERS => '0'); - ELSE + ELSE -- Clear valid flag when master interface is ready IF m_axis_tready = '1' THEN m_axis_tvalid_int <= '0'; @@ -54,11 +56,11 @@ BEGIN -- Handle the data flow IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN -- Check if the input data is within the bounds else saturate - IF signed(s_axis_tdata) > to_signed(HIGHER_BOUND, s_axis_tdata'length) THEN - m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(HIGHER_BOUND, TDATA_WIDTH)); + IF signed(s_axis_tdata) > signed(HIGHER_BOUND_VEC) THEN + m_axis_tdata <= HIGHER_BOUND_VEC; - ELSIF signed(s_axis_tdata) < to_signed(LOWER_BOUND, s_axis_tdata'length) THEN - m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(LOWER_BOUND, TDATA_WIDTH)); + ELSIF signed(s_axis_tdata) < signed(LOWER_BOUND_VEC) THEN + m_axis_tdata <= LOWER_BOUND_VEC; ELSE m_axis_tdata <= STD_LOGIC_VECTOR(resize(signed(s_axis_tdata), TDATA_WIDTH)); diff --git a/LAB3/vivado/volume_multiplier/volume_multiplier.xpr b/LAB3/vivado/volume_multiplier/volume_multiplier.xpr index fe41755..a4cab43 100644 --- a/LAB3/vivado/volume_multiplier/volume_multiplier.xpr +++ b/LAB3/vivado/volume_multiplier/volume_multiplier.xpr @@ -47,7 +47,7 @@