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Update to work at 180MHz

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This commit is contained in:
Davide Cavagnola
2025-05-26 14:08:08 +02:00
parent 0b9c06d11e
commit d4f2772027
12 changed files with 1028 additions and 408 deletions
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60
LAB3/src/LFO.vhd
View File

@@ -42,18 +42,24 @@ ARCHITECTURE Behavioral OF LFO IS
CONSTANT LFO_CLK_CYCLES_MIN : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1)); -- 53_920 clk cycles
CONSTANT LFO_CLK_CYCLES_MAX : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES + ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1); -- 145_990 clk cycles
SIGNAL step_clk_cycles_delta : INTEGER RANGE - 2 ** (JOYSTICK_LENGHT - 1) * ADJUSTMENT_FACTOR TO (2 ** (JOYSTICK_LENGHT - 1) - 1) * ADJUSTMENT_FACTOR := 0;
SIGNAL step_clk_cycles : INTEGER RANGE LFO_CLK_CYCLES_MIN TO LFO_CLK_CYCLES_MAX := LFO_COUNTER_BASE_CLK_CYCLES;
SIGNAL step_counter : INTEGER RANGE 0 TO LFO_CLK_CYCLES_MAX := 0;
SIGNAL tri_counter : SIGNED(TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
SIGNAL direction_up : STD_LOGIC := '1';
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
SIGNAL m_axis_tdata_temp : SIGNED(CHANNEL_LENGHT + TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
s_axis_tready <= s_axis_tready_int;
-- Optimized single process for LFO step and triangular waveform generation
PROCESS (aclk)
@@ -68,7 +74,8 @@ BEGIN
ELSE
-- Set the step_clk_cycles based on the joystick input
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (to_integer(unsigned(lfo_period)) - JSTK_CENTER_VALUE);
step_clk_cycles_delta <= (to_integer(unsigned(lfo_period)) - JSTK_CENTER_VALUE) * ADJUSTMENT_FACTOR;
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - step_clk_cycles_delta;
IF lfo_enable = '1' THEN
@@ -110,6 +117,9 @@ BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
s_axis_tlast_reg <= '0';
s_axis_tready_int <= '0';
m_axis_tdata_temp <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
@@ -119,28 +129,48 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
-- Data output logic
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
m_axis_tdata_temp,
TRIANGULAR_COUNTER_LENGHT
),
CHANNEL_LENGHT
)
);
m_axis_tlast <= s_axis_tlast_reg;
m_axis_tvalid_int <= '1';
trigger <= '0';
END IF;
-- Data input logic
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF lfo_enable = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
signed(s_axis_tdata) * tri_counter,
TRIANGULAR_COUNTER_LENGHT
),
CHANNEL_LENGHT
)
);
m_axis_tdata_temp <= signed(s_axis_tdata) * tri_counter;
s_axis_tlast_reg <= s_axis_tlast;
ELSE
m_axis_tdata <= s_axis_tdata;
m_axis_tdata_temp <= shift_left(
resize(
signed(s_axis_tdata),
m_axis_tdata_temp'length
),
TRIANGULAR_COUNTER_LENGHT
);
s_axis_tlast_reg <= s_axis_tlast;
END IF;
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
trigger <= '1';
END IF;
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
END IF;
END IF;

35
LAB3/src/all_pass_filter.vhd
View File

@@ -24,6 +24,11 @@ END all_pass_filter;
ARCHITECTURE Behavioral OF all_pass_filter IS
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
SIGNAL m_axis_tdata_temp : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
@@ -34,13 +39,19 @@ BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
s_axis_tready <= s_axis_tready_int;
PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
-- Reset all internal signals
trigger <= '0';
s_axis_tlast_reg <= '0';
s_axis_tready_int <= '0';
m_axis_tdata_temp <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
@@ -50,15 +61,27 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
-- Handle data transfer
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
m_axis_tdata <= s_axis_tdata;
-- Data output logic
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tdata <= m_axis_tdata_temp;
m_axis_tlast <= s_axis_tlast_reg;
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
trigger <= '0';
END IF;
-- Data input logic
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
s_axis_tlast_reg <= s_axis_tlast;
m_axis_tdata_temp <= s_axis_tdata;
trigger <= '1';
END IF;
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
END IF;
END IF;

74
LAB3/src/moving_average_filter.vhd
View File

@@ -41,13 +41,19 @@ ARCHITECTURE Behavioral OF moving_average_filter IS
SIGNAL sum_sx : signed(TDATA_WIDTH + FILTER_ORDER_POWER - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_ptr_sx : INTEGER RANGE 0 TO FILTER_ORDER - 1 := 0;
-- Trigger signal to indicate when to output data
SIGNAL trigger : STD_LOGIC := '0';
-- Output signals
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
s_axis_tready <= s_axis_tready_int;
PROCESS (aclk)
BEGIN
@@ -62,6 +68,8 @@ BEGIN
wr_ptr_dx <= 0;
wr_ptr_sx <= 0;
s_axis_tlast_reg <= '0';
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
@@ -71,10 +79,41 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
-- Get and process data
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
-- Data output logic
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
IF s_axis_tlast_reg = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
sum_dx,
FILTER_ORDER_POWER
),
m_axis_tdata'length
)
);
IF s_axis_tlast = '1' THEN
ELSE
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
sum_sx,
FILTER_ORDER_POWER
),
m_axis_tdata'length
)
);
END IF;
m_axis_tlast <= s_axis_tlast_reg;
m_axis_tvalid_int <= '1';
trigger <= '0';
END IF;
-- Data input logic
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF s_axis_tlast = '1' THEN
-- Right channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
samples_dx(wr_ptr_dx) <= signed(s_axis_tdata);
@@ -85,16 +124,7 @@ BEGIN
-- Update the sum_dx removing the oldest sample and adding the new one
sum_dx <= sum_dx - samples_dx(wr_ptr_dx) + signed(s_axis_tdata);
-- Calculate the average and send it to the master interface
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
sum_dx - samples_dx(wr_ptr_dx) + signed(s_axis_tdata),
FILTER_ORDER_POWER
),
m_axis_tdata'length
)
);
s_axis_tlast_reg <= s_axis_tlast;
ELSE
-- Left channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
@@ -106,23 +136,15 @@ BEGIN
-- Update the sum_dx removing the oldest sample and adding the new one
sum_sx <= sum_sx - samples_sx(wr_ptr_sx) + signed(s_axis_tdata);
-- Calculate the average and send it to the master interface
m_axis_tdata <= STD_LOGIC_VECTOR(
resize(
shift_right(
sum_sx - samples_sx(wr_ptr_sx) + signed(s_axis_tdata),
FILTER_ORDER_POWER
),
m_axis_tdata'length
)
);
s_axis_tlast_reg <= s_axis_tlast;
END IF;
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
trigger <= '1';
END IF;
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
END IF;
END IF;