Update to work at 180MHz
This commit is contained in:
@@ -1,8 +1,8 @@
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Fri May 23 16:56:48 2025
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--Date : Mon May 26 12:51:36 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Host : DavideASUS running 64-bit major release (build 9200)
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--Command : generate_target lab_3_wrapper.bd
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--Command : generate_target lab_3_wrapper.bd
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--Design : lab_3_wrapper
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--Design : lab_3_wrapper
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--Purpose : IP block netlist
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--Purpose : IP block netlist
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@@ -48,6 +48,7 @@ architecture STRUCTURE of lab_3_wrapper is
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tx_mclk_0 : out STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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lfo_enable : in STD_LOGIC;
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lfo_enable : in STD_LOGIC;
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effect : in STD_LOGIC;
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effect : in STD_LOGIC;
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LED : out STD_LOGIC_VECTOR ( 15 downto 0 );
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SPI_M_0_sck_t : out STD_LOGIC;
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SPI_M_0_sck_t : out STD_LOGIC;
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SPI_M_0_io1_o : out STD_LOGIC;
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SPI_M_0_io1_o : out STD_LOGIC;
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SPI_M_0_ss_t : out STD_LOGIC;
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SPI_M_0_ss_t : out STD_LOGIC;
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@@ -59,8 +60,7 @@ architecture STRUCTURE of lab_3_wrapper is
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SPI_M_0_sck_o : out STD_LOGIC;
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SPI_M_0_sck_o : out STD_LOGIC;
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SPI_M_0_ss_i : in STD_LOGIC;
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SPI_M_0_ss_i : in STD_LOGIC;
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SPI_M_0_io1_i : in STD_LOGIC;
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SPI_M_0_io1_i : in STD_LOGIC;
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SPI_M_0_io0_i : in STD_LOGIC;
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SPI_M_0_io0_i : in STD_LOGIC
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LED : out STD_LOGIC_VECTOR ( 15 downto 0 )
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);
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);
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end component lab_3;
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end component lab_3;
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component IOBUF is
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component IOBUF is
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@@ -6,8 +6,7 @@
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"name": "lab_3",
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"name": "lab_3",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "None",
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"synth_flow_mode": "None",
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"tool_version": "2020.2",
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"tool_version": "2020.2"
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"validated": "true"
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},
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},
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"design_tree": {
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"design_tree": {
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"clk_wiz_0": "",
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"clk_wiz_0": "",
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@@ -25,8 +24,8 @@
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"effect_selector_0": "",
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"effect_selector_0": "",
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"led_level_controller_0": "",
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"led_level_controller_0": "",
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"led_controller_0": "",
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"led_controller_0": "",
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"moving_average_filte_0": "",
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"mute_controller_0": "",
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"mute_controller_0": "",
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"moving_average_filte_0": "",
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"LFO_0": ""
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"LFO_0": ""
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},
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},
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"interface_ports": {
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"interface_ports": {
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@@ -40,21 +39,9 @@
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"type": "clk",
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"type": "clk",
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"direction": "I",
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"direction": "I",
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"parameters": {
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"parameters": {
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"CLK_DOMAIN": {
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"value": "lab_3_sys_clock",
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"value_src": "default"
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000"
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"value": "100000000"
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},
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},
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"FREQ_TOLERANCE_HZ": {
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"value": "0",
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"value_src": "default"
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},
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"PHASE": {
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"PHASE": {
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"value": "0.000"
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"value": "0.000"
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}
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}
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@@ -64,10 +51,6 @@
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"type": "rst",
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"type": "rst",
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"direction": "I",
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"direction": "I",
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"parameters": {
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"POLARITY": {
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"value": "ACTIVE_HIGH"
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"value": "ACTIVE_HIGH"
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}
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}
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@@ -117,19 +100,19 @@
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"inst_hier_path": "clk_wiz_0",
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"inst_hier_path": "clk_wiz_0",
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"parameters": {
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"parameters": {
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"CLKOUT1_JITTER": {
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"CLKOUT1_JITTER": {
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"value": "149.337"
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"value": "224.262"
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},
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},
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"CLKOUT1_PHASE_ERROR": {
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"CLKOUT1_PHASE_ERROR": {
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"value": "122.577"
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"value": "296.868"
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},
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},
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"CLKOUT1_REQUESTED_OUT_FREQ": {
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"CLKOUT1_REQUESTED_OUT_FREQ": {
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"value": "100"
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"value": "180"
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},
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},
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"CLKOUT2_JITTER": {
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"CLKOUT2_JITTER": {
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"value": "201.826"
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"value": "316.348"
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},
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},
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"CLKOUT2_PHASE_ERROR": {
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"CLKOUT2_PHASE_ERROR": {
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"value": "122.577"
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"value": "296.868"
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},
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},
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"CLKOUT2_REQUESTED_OUT_FREQ": {
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"CLKOUT2_REQUESTED_OUT_FREQ": {
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"value": "22.579"
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"value": "22.579"
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@@ -141,16 +124,16 @@
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"value": "sys_clock"
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"value": "sys_clock"
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},
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},
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"MMCM_CLKFBOUT_MULT_F": {
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"MMCM_CLKFBOUT_MULT_F": {
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"value": "7.000"
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"value": "49.500"
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},
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},
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"MMCM_CLKOUT0_DIVIDE_F": {
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"MMCM_CLKOUT0_DIVIDE_F": {
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"value": "7.000"
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"value": "5.500"
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},
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},
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"MMCM_CLKOUT1_DIVIDE": {
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"MMCM_CLKOUT1_DIVIDE": {
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"value": "31"
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"value": "44"
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},
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},
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"MMCM_DIVCLK_DIVIDE": {
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"MMCM_DIVCLK_DIVIDE": {
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"value": "1"
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"value": "5"
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},
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},
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"NUM_OUT_CLKS": {
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"NUM_OUT_CLKS": {
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"value": "2"
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"value": "2"
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@@ -201,7 +184,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -252,7 +235,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -305,7 +288,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -415,7 +398,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -481,7 +464,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -521,7 +504,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -630,7 +613,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -700,7 +683,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -748,7 +731,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -826,7 +809,7 @@
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"value_src": "constant"
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"value_src": "constant"
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},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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"value": "100000000",
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"value": "180000000",
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||||||
"value_src": "ip_prop"
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"value_src": "ip_prop"
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},
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},
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"PHASE": {
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"PHASE": {
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@@ -896,7 +879,7 @@
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"value_src": "constant"
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"value_src": "constant"
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||||||
},
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},
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"FREQ_HZ": {
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"FREQ_HZ": {
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||||||
"value": "100000000",
|
"value": "180000000",
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||||||
"value_src": "ip_prop"
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"value_src": "ip_prop"
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||||||
},
|
},
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||||||
"PHASE": {
|
"PHASE": {
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@@ -944,7 +927,7 @@
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"value_src": "constant"
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"value_src": "constant"
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||||||
},
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},
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||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
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||||||
"value": "100000000",
|
"value": "180000000",
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||||||
"value_src": "ip_prop"
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"value_src": "ip_prop"
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||||||
},
|
},
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"PHASE": {
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"PHASE": {
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@@ -994,7 +977,7 @@
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"value_src": "constant"
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"value_src": "constant"
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||||||
},
|
},
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||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1100,7 +1083,7 @@
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"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
},
|
||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1148,7 +1131,7 @@
|
|||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
},
|
||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1212,200 +1195,6 @@
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
"moving_average_filte_0": {
|
|
||||||
"vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
|
|
||||||
"xci_name": "lab_3_moving_average_filte_0_0",
|
|
||||||
"xci_path": "ip\\lab_3_moving_average_filte_0_0\\lab_3_moving_average_filte_0_0.xci",
|
|
||||||
"inst_hier_path": "moving_average_filte_0",
|
|
||||||
"reference_info": {
|
|
||||||
"ref_type": "hdl",
|
|
||||||
"ref_name": "moving_average_filter_en",
|
|
||||||
"boundary_crc": "0x0"
|
|
||||||
},
|
|
||||||
"interface_ports": {
|
|
||||||
"m_axis": {
|
|
||||||
"mode": "Master",
|
|
||||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
|
||||||
"parameters": {
|
|
||||||
"TDATA_NUM_BYTES": {
|
|
||||||
"value": "3",
|
|
||||||
"value_src": "auto"
|
|
||||||
},
|
|
||||||
"TDEST_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"TID_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"TUSER_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TREADY": {
|
|
||||||
"value": "1",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TSTRB": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TKEEP": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TLAST": {
|
|
||||||
"value": "1",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"TDATA": {
|
|
||||||
"physical_name": "m_axis_tdata",
|
|
||||||
"direction": "O",
|
|
||||||
"left": "23",
|
|
||||||
"right": "0"
|
|
||||||
},
|
|
||||||
"TLAST": {
|
|
||||||
"physical_name": "m_axis_tlast",
|
|
||||||
"direction": "O"
|
|
||||||
},
|
|
||||||
"TVALID": {
|
|
||||||
"physical_name": "m_axis_tvalid",
|
|
||||||
"direction": "O"
|
|
||||||
},
|
|
||||||
"TREADY": {
|
|
||||||
"physical_name": "m_axis_tready",
|
|
||||||
"direction": "I"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"s_axis": {
|
|
||||||
"mode": "Slave",
|
|
||||||
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
|
||||||
"parameters": {
|
|
||||||
"TDATA_NUM_BYTES": {
|
|
||||||
"value": "3",
|
|
||||||
"value_src": "auto"
|
|
||||||
},
|
|
||||||
"TDEST_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"TID_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"TUSER_WIDTH": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TREADY": {
|
|
||||||
"value": "1",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TSTRB": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TKEEP": {
|
|
||||||
"value": "0",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"HAS_TLAST": {
|
|
||||||
"value": "1",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"port_maps": {
|
|
||||||
"TDATA": {
|
|
||||||
"physical_name": "s_axis_tdata",
|
|
||||||
"direction": "I",
|
|
||||||
"left": "23",
|
|
||||||
"right": "0"
|
|
||||||
},
|
|
||||||
"TLAST": {
|
|
||||||
"physical_name": "s_axis_tlast",
|
|
||||||
"direction": "I"
|
|
||||||
},
|
|
||||||
"TVALID": {
|
|
||||||
"physical_name": "s_axis_tvalid",
|
|
||||||
"direction": "I"
|
|
||||||
},
|
|
||||||
"TREADY": {
|
|
||||||
"physical_name": "s_axis_tready",
|
|
||||||
"direction": "O"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"ports": {
|
|
||||||
"aclk": {
|
|
||||||
"type": "clk",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"ASSOCIATED_BUSIF": {
|
|
||||||
"value": "m_axis:s_axis",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"ASSOCIATED_RESET": {
|
|
||||||
"value": "aresetn",
|
|
||||||
"value_src": "constant"
|
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"aresetn": {
|
|
||||||
"type": "rst",
|
|
||||||
"direction": "I",
|
|
||||||
"parameters": {
|
|
||||||
"POLARITY": {
|
|
||||||
"value": "ACTIVE_LOW",
|
|
||||||
"value_src": "constant"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"enable_filter": {
|
|
||||||
"direction": "I"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"mute_controller_0": {
|
"mute_controller_0": {
|
||||||
"vlnv": "xilinx.com:module_ref:mute_controller:1.0",
|
"vlnv": "xilinx.com:module_ref:mute_controller:1.0",
|
||||||
"xci_name": "lab_3_mute_controller_0_0",
|
"xci_name": "lab_3_mute_controller_0_0",
|
||||||
@@ -1454,7 +1243,7 @@
|
|||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
},
|
||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1524,7 +1313,7 @@
|
|||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
},
|
||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1572,7 +1361,7 @@
|
|||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
},
|
||||||
"FREQ_HZ": {
|
"FREQ_HZ": {
|
||||||
"value": "100000000",
|
"value": "180000000",
|
||||||
"value_src": "ip_prop"
|
"value_src": "ip_prop"
|
||||||
},
|
},
|
||||||
"PHASE": {
|
"PHASE": {
|
||||||
@@ -1600,6 +1389,164 @@
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
|
"moving_average_filte_0": {
|
||||||
|
"vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
|
||||||
|
"xci_name": "lab_3_moving_average_filte_0_0",
|
||||||
|
"xci_path": "ip\\lab_3_moving_average_filte_0_0\\lab_3_moving_average_filte_0_0.xci",
|
||||||
|
"inst_hier_path": "moving_average_filte_0",
|
||||||
|
"reference_info": {
|
||||||
|
"ref_type": "hdl",
|
||||||
|
"ref_name": "moving_average_filter_en",
|
||||||
|
"boundary_crc": "0x0"
|
||||||
|
},
|
||||||
|
"interface_ports": {
|
||||||
|
"m_axis": {
|
||||||
|
"mode": "Master",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "3",
|
||||||
|
"value_src": "auto"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "m_axis_tdata",
|
||||||
|
"direction": "O",
|
||||||
|
"left": "23",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TLAST": {
|
||||||
|
"physical_name": "m_axis_tlast",
|
||||||
|
"direction": "O"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "m_axis_tvalid",
|
||||||
|
"direction": "O"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "m_axis_tready",
|
||||||
|
"direction": "I"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"s_axis": {
|
||||||
|
"mode": "Slave",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "3",
|
||||||
|
"value_src": "auto"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "s_axis_tdata",
|
||||||
|
"direction": "I",
|
||||||
|
"left": "23",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TLAST": {
|
||||||
|
"physical_name": "s_axis_tlast",
|
||||||
|
"direction": "I"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "s_axis_tvalid",
|
||||||
|
"direction": "I"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "s_axis_tready",
|
||||||
|
"direction": "O"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ports": {
|
||||||
|
"aclk": {
|
||||||
|
"type": "clk",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": {
|
||||||
|
"value": "m_axis:s_axis",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"ASSOCIATED_RESET": {
|
||||||
|
"value": "aresetn",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn": {
|
||||||
|
"type": "rst",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": {
|
||||||
|
"value": "ACTIVE_LOW",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"enable_filter": {
|
||||||
|
"direction": "I"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
"LFO_0": {
|
"LFO_0": {
|
||||||
"vlnv": "xilinx.com:module_ref:LFO:1.0",
|
"vlnv": "xilinx.com:module_ref:LFO:1.0",
|
||||||
"xci_name": "lab_3_LFO_0_0",
|
"xci_name": "lab_3_LFO_0_0",
|
||||||
@@ -1651,18 +1598,6 @@
|
|||||||
"HAS_TLAST": {
|
"HAS_TLAST": {
|
||||||
"value": "1",
|
"value": "1",
|
||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
"port_maps": {
|
"port_maps": {
|
||||||
@@ -1721,18 +1656,6 @@
|
|||||||
"HAS_TLAST": {
|
"HAS_TLAST": {
|
||||||
"value": "1",
|
"value": "1",
|
||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
"port_maps": {
|
"port_maps": {
|
||||||
@@ -1769,18 +1692,6 @@
|
|||||||
"ASSOCIATED_RESET": {
|
"ASSOCIATED_RESET": {
|
||||||
"value": "aresetn",
|
"value": "aresetn",
|
||||||
"value_src": "constant"
|
"value_src": "constant"
|
||||||
},
|
|
||||||
"FREQ_HZ": {
|
|
||||||
"value": "100000000",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"PHASE": {
|
|
||||||
"value": "0.0",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
},
|
|
||||||
"CLK_DOMAIN": {
|
|
||||||
"value": "/clk_wiz_0_clk_out1",
|
|
||||||
"value_src": "ip_prop"
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
@@ -1812,36 +1723,12 @@
|
|||||||
"axi4stream_spi_master_0/SPI_M"
|
"axi4stream_spi_master_0/SPI_M"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
"axis_broadcaster_0_M00_AXIS": {
|
|
||||||
"interface_ports": [
|
|
||||||
"axis_broadcaster_0/M00_AXIS",
|
|
||||||
"axis_dual_i2s_0/s_axis"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"mute_controller_0_m_axis": {
|
|
||||||
"interface_ports": [
|
|
||||||
"mute_controller_0/m_axis",
|
|
||||||
"axis_broadcaster_0/S_AXIS"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"moving_average_filte_0_m_axis": {
|
|
||||||
"interface_ports": [
|
|
||||||
"balance_controller_0/s_axis",
|
|
||||||
"moving_average_filte_0/m_axis"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"balance_controller_0_m_axis": {
|
"balance_controller_0_m_axis": {
|
||||||
"interface_ports": [
|
"interface_ports": [
|
||||||
"balance_controller_0/m_axis",
|
"balance_controller_0/m_axis",
|
||||||
"volume_controller_0/s_axis"
|
"volume_controller_0/s_axis"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
"volume_controller_0_m_axis": {
|
|
||||||
"interface_ports": [
|
|
||||||
"volume_controller_0/m_axis",
|
|
||||||
"LFO_0/s_axis"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"axis_broadcaster_0_M01_AXIS": {
|
"axis_broadcaster_0_M01_AXIS": {
|
||||||
"interface_ports": [
|
"interface_ports": [
|
||||||
"axis_broadcaster_0/M01_AXIS",
|
"axis_broadcaster_0/M01_AXIS",
|
||||||
@@ -1854,18 +1741,42 @@
|
|||||||
"moving_average_filte_0/s_axis"
|
"moving_average_filte_0/s_axis"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
"digilent_jstk2_0_m_axis": {
|
|
||||||
"interface_ports": [
|
|
||||||
"digilent_jstk2_0/m_axis",
|
|
||||||
"axi4stream_spi_master_0/S_AXIS"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
"axi4stream_spi_master_0_M_AXIS": {
|
"axi4stream_spi_master_0_M_AXIS": {
|
||||||
"interface_ports": [
|
"interface_ports": [
|
||||||
"axi4stream_spi_master_0/M_AXIS",
|
"axi4stream_spi_master_0/M_AXIS",
|
||||||
"digilent_jstk2_0/s_axis"
|
"digilent_jstk2_0/s_axis"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
"mute_controller_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"mute_controller_0/m_axis",
|
||||||
|
"axis_broadcaster_0/S_AXIS"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"moving_average_filte_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"balance_controller_0/s_axis",
|
||||||
|
"moving_average_filte_0/m_axis"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"volume_controller_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"volume_controller_0/m_axis",
|
||||||
|
"LFO_0/s_axis"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"axis_broadcaster_0_M00_AXIS": {
|
||||||
|
"interface_ports": [
|
||||||
|
"axis_broadcaster_0/M00_AXIS",
|
||||||
|
"axis_dual_i2s_0/s_axis"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"digilent_jstk2_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"digilent_jstk2_0/m_axis",
|
||||||
|
"axi4stream_spi_master_0/S_AXIS"
|
||||||
|
]
|
||||||
|
},
|
||||||
"LFO_0_m_axis": {
|
"LFO_0_m_axis": {
|
||||||
"interface_ports": [
|
"interface_ports": [
|
||||||
"LFO_0/m_axis",
|
"LFO_0/m_axis",
|
||||||
@@ -1895,8 +1806,8 @@
|
|||||||
"balance_controller_0/aclk",
|
"balance_controller_0/aclk",
|
||||||
"effect_selector_0/aclk",
|
"effect_selector_0/aclk",
|
||||||
"led_level_controller_0/aclk",
|
"led_level_controller_0/aclk",
|
||||||
"moving_average_filte_0/aclk",
|
|
||||||
"mute_controller_0/aclk",
|
"mute_controller_0/aclk",
|
||||||
|
"moving_average_filte_0/aclk",
|
||||||
"LFO_0/aclk"
|
"LFO_0/aclk"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
@@ -1934,8 +1845,8 @@
|
|||||||
"balance_controller_0/aresetn",
|
"balance_controller_0/aresetn",
|
||||||
"effect_selector_0/aresetn",
|
"effect_selector_0/aresetn",
|
||||||
"led_level_controller_0/aresetn",
|
"led_level_controller_0/aresetn",
|
||||||
"moving_average_filte_0/aresetn",
|
|
||||||
"mute_controller_0/aresetn",
|
"mute_controller_0/aresetn",
|
||||||
|
"moving_average_filte_0/aresetn",
|
||||||
"LFO_0/aresetn"
|
"LFO_0/aresetn"
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
|
|||||||
@@ -21,22 +21,22 @@
|
|||||||
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
||||||
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
||||||
<node id="n0">
|
<node id="n0">
|
||||||
<data key="VM">lab_3</data>
|
|
||||||
<data key="VT">BC</data>
|
|
||||||
</node>
|
|
||||||
<node id="n1">
|
|
||||||
<data key="TU">active</data>
|
<data key="TU">active</data>
|
||||||
<data key="VH">2</data>
|
<data key="VH">2</data>
|
||||||
<data key="VT">PM</data>
|
<data key="VT">PM</data>
|
||||||
</node>
|
</node>
|
||||||
|
<node id="n1">
|
||||||
|
<data key="VM">lab_3</data>
|
||||||
|
<data key="VT">BC</data>
|
||||||
|
</node>
|
||||||
<node id="n2">
|
<node id="n2">
|
||||||
<data key="VH">2</data>
|
<data key="VH">2</data>
|
||||||
<data key="VM">lab_3</data>
|
<data key="VM">lab_3</data>
|
||||||
<data key="VT">VR</data>
|
<data key="VT">VR</data>
|
||||||
</node>
|
</node>
|
||||||
<edge id="e0" source="n0" target="n2">
|
<edge id="e0" source="n1" target="n2">
|
||||||
</edge>
|
</edge>
|
||||||
<edge id="e1" source="n2" target="n1">
|
<edge id="e1" source="n2" target="n0">
|
||||||
</edge>
|
</edge>
|
||||||
</graph>
|
</graph>
|
||||||
</graphml>
|
</graphml>
|
||||||
|
|||||||
117
LAB3/sim/tb_LFO.vhd
Normal file
117
LAB3/sim/tb_LFO.vhd
Normal file
@@ -0,0 +1,117 @@
|
|||||||
|
-- filepath: c:\DESD\LAB3\sim\tb_LFO.vhd
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
ENTITY tb_LFO IS
|
||||||
|
END tb_LFO;
|
||||||
|
|
||||||
|
ARCHITECTURE sim OF tb_LFO IS
|
||||||
|
|
||||||
|
CONSTANT CHANNEL_LENGHT : INTEGER := 24;
|
||||||
|
CONSTANT JOYSTICK_LENGHT : INTEGER := 10;
|
||||||
|
CONSTANT TRIANGULAR_COUNTER_LENGHT: INTEGER := 10;
|
||||||
|
CONSTANT CLK_PERIOD_NS : INTEGER := 10;
|
||||||
|
|
||||||
|
SIGNAL aclk : STD_LOGIC := '0';
|
||||||
|
SIGNAL aresetn : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
SIGNAL lfo_period : STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 DOWNTO 0) := (OTHERS => '0');
|
||||||
|
SIGNAL lfo_enable : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
|
||||||
|
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0) := (OTHERS => '0');
|
||||||
|
SIGNAL s_axis_tlast : STD_LOGIC := '0';
|
||||||
|
SIGNAL s_axis_tready : STD_LOGIC;
|
||||||
|
|
||||||
|
SIGNAL m_axis_tvalid : STD_LOGIC;
|
||||||
|
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
|
||||||
|
SIGNAL m_axis_tlast : STD_LOGIC;
|
||||||
|
SIGNAL m_axis_tready : STD_LOGIC := '1';
|
||||||
|
|
||||||
|
-- DUT
|
||||||
|
COMPONENT LFO
|
||||||
|
GENERIC (
|
||||||
|
CHANNEL_LENGHT : INTEGER := 24;
|
||||||
|
JOYSTICK_LENGHT : INTEGER := 10;
|
||||||
|
CLK_PERIOD_NS : INTEGER := 10;
|
||||||
|
TRIANGULAR_COUNTER_LENGHT : INTEGER := 10
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
aclk : IN STD_LOGIC;
|
||||||
|
aresetn : IN STD_LOGIC;
|
||||||
|
lfo_period : IN STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 DOWNTO 0);
|
||||||
|
lfo_enable : IN STD_LOGIC;
|
||||||
|
s_axis_tvalid : IN STD_LOGIC;
|
||||||
|
s_axis_tdata : IN STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
|
||||||
|
s_axis_tlast : IN STD_LOGIC;
|
||||||
|
s_axis_tready : OUT STD_LOGIC;
|
||||||
|
m_axis_tvalid : OUT STD_LOGIC;
|
||||||
|
m_axis_tdata : OUT STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
|
||||||
|
m_axis_tlast : OUT STD_LOGIC;
|
||||||
|
m_axis_tready : IN STD_LOGIC
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
|
||||||
|
BEGIN
|
||||||
|
|
||||||
|
-- Clock generation
|
||||||
|
clk_proc : PROCESS
|
||||||
|
BEGIN
|
||||||
|
aclk <= '0';
|
||||||
|
WAIT FOR 5 ns;
|
||||||
|
aclk <= '1';
|
||||||
|
WAIT FOR 5 ns;
|
||||||
|
END PROCESS;
|
||||||
|
|
||||||
|
-- DUT instantiation
|
||||||
|
dut: LFO
|
||||||
|
GENERIC MAP (
|
||||||
|
CHANNEL_LENGHT => CHANNEL_LENGHT,
|
||||||
|
JOYSTICK_LENGHT => JOYSTICK_LENGHT,
|
||||||
|
CLK_PERIOD_NS => CLK_PERIOD_NS,
|
||||||
|
TRIANGULAR_COUNTER_LENGHT => TRIANGULAR_COUNTER_LENGHT
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
aclk => aclk,
|
||||||
|
aresetn => aresetn,
|
||||||
|
lfo_period => lfo_period,
|
||||||
|
lfo_enable => lfo_enable,
|
||||||
|
s_axis_tvalid => s_axis_tvalid,
|
||||||
|
s_axis_tdata => s_axis_tdata,
|
||||||
|
s_axis_tlast => s_axis_tlast,
|
||||||
|
s_axis_tready => s_axis_tready,
|
||||||
|
m_axis_tvalid => m_axis_tvalid,
|
||||||
|
m_axis_tdata => m_axis_tdata,
|
||||||
|
m_axis_tlast => m_axis_tlast,
|
||||||
|
m_axis_tready => m_axis_tready
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Stimulus process
|
||||||
|
stim_proc : PROCESS
|
||||||
|
VARIABLE data_cnt : INTEGER := 0;
|
||||||
|
BEGIN
|
||||||
|
-- Reset
|
||||||
|
aresetn <= '0';
|
||||||
|
WAIT FOR 20 ns;
|
||||||
|
aresetn <= '1';
|
||||||
|
WAIT FOR 10 ns;
|
||||||
|
|
||||||
|
-- Imposta parametri iniziali
|
||||||
|
lfo_enable <= '1'; -- o '0' se vuoi testare la modalit<69> bypass
|
||||||
|
lfo_period <= std_logic_vector(to_unsigned(512, JOYSTICK_LENGHT)); -- Valore fisso
|
||||||
|
|
||||||
|
-- Loop infinito: invia dati ad ogni ciclo di clock
|
||||||
|
WHILE TRUE LOOP
|
||||||
|
WAIT UNTIL rising_edge(aclk);
|
||||||
|
s_axis_tdata <= std_logic_vector(to_signed(data_cnt, CHANNEL_LENGHT));
|
||||||
|
s_axis_tvalid <= '1';
|
||||||
|
s_axis_tlast <= '0'; -- Puoi impostare a '1' ogni N campioni se vuoi testare tlast
|
||||||
|
|
||||||
|
IF s_axis_tready = '1' THEN
|
||||||
|
data_cnt := data_cnt + 1;
|
||||||
|
END IF;
|
||||||
|
END LOOP;
|
||||||
|
END PROCESS;
|
||||||
|
|
||||||
|
END sim;
|
||||||
@@ -42,18 +42,24 @@ ARCHITECTURE Behavioral OF LFO IS
|
|||||||
CONSTANT LFO_CLK_CYCLES_MIN : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1)); -- 53_920 clk cycles
|
CONSTANT LFO_CLK_CYCLES_MIN : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1)); -- 53_920 clk cycles
|
||||||
CONSTANT LFO_CLK_CYCLES_MAX : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES + ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1); -- 145_990 clk cycles
|
CONSTANT LFO_CLK_CYCLES_MAX : INTEGER := LFO_COUNTER_BASE_CLK_CYCLES + ADJUSTMENT_FACTOR * (2 ** (JOYSTICK_LENGHT - 1) - 1); -- 145_990 clk cycles
|
||||||
|
|
||||||
|
SIGNAL step_clk_cycles_delta : INTEGER RANGE - 2 ** (JOYSTICK_LENGHT - 1) * ADJUSTMENT_FACTOR TO (2 ** (JOYSTICK_LENGHT - 1) - 1) * ADJUSTMENT_FACTOR := 0;
|
||||||
SIGNAL step_clk_cycles : INTEGER RANGE LFO_CLK_CYCLES_MIN TO LFO_CLK_CYCLES_MAX := LFO_COUNTER_BASE_CLK_CYCLES;
|
SIGNAL step_clk_cycles : INTEGER RANGE LFO_CLK_CYCLES_MIN TO LFO_CLK_CYCLES_MAX := LFO_COUNTER_BASE_CLK_CYCLES;
|
||||||
SIGNAL step_counter : INTEGER RANGE 0 TO LFO_CLK_CYCLES_MAX := 0;
|
SIGNAL step_counter : INTEGER RANGE 0 TO LFO_CLK_CYCLES_MAX := 0;
|
||||||
SIGNAL tri_counter : SIGNED(TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
|
SIGNAL tri_counter : SIGNED(TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
|
||||||
SIGNAL direction_up : STD_LOGIC := '1';
|
SIGNAL direction_up : STD_LOGIC := '1';
|
||||||
|
|
||||||
|
SIGNAL trigger : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
|
||||||
|
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
|
||||||
|
SIGNAL m_axis_tdata_temp : SIGNED(CHANNEL_LENGHT + TRIANGULAR_COUNTER_LENGHT DOWNTO 0) := (OTHERS => '0');
|
||||||
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
|
|
||||||
-- Assigning the output signals
|
-- Assigning the output signals
|
||||||
m_axis_tvalid <= m_axis_tvalid_int;
|
m_axis_tvalid <= m_axis_tvalid_int;
|
||||||
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
|
s_axis_tready <= s_axis_tready_int;
|
||||||
|
|
||||||
-- Optimized single process for LFO step and triangular waveform generation
|
-- Optimized single process for LFO step and triangular waveform generation
|
||||||
PROCESS (aclk)
|
PROCESS (aclk)
|
||||||
@@ -68,7 +74,8 @@ BEGIN
|
|||||||
|
|
||||||
ELSE
|
ELSE
|
||||||
-- Set the step_clk_cycles based on the joystick input
|
-- Set the step_clk_cycles based on the joystick input
|
||||||
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - ADJUSTMENT_FACTOR * (to_integer(unsigned(lfo_period)) - JSTK_CENTER_VALUE);
|
step_clk_cycles_delta <= (to_integer(unsigned(lfo_period)) - JSTK_CENTER_VALUE) * ADJUSTMENT_FACTOR;
|
||||||
|
step_clk_cycles <= LFO_COUNTER_BASE_CLK_CYCLES - step_clk_cycles_delta;
|
||||||
|
|
||||||
IF lfo_enable = '1' THEN
|
IF lfo_enable = '1' THEN
|
||||||
|
|
||||||
@@ -110,6 +117,9 @@ BEGIN
|
|||||||
IF rising_edge(aclk) THEN
|
IF rising_edge(aclk) THEN
|
||||||
|
|
||||||
IF aresetn = '0' THEN
|
IF aresetn = '0' THEN
|
||||||
|
s_axis_tlast_reg <= '0';
|
||||||
|
s_axis_tready_int <= '0';
|
||||||
|
m_axis_tdata_temp <= (OTHERS => '0');
|
||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
m_axis_tlast <= '0';
|
m_axis_tlast <= '0';
|
||||||
|
|
||||||
@@ -119,28 +129,48 @@ BEGIN
|
|||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
-- Data output logic
|
||||||
|
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
|
||||||
|
m_axis_tdata <= STD_LOGIC_VECTOR(
|
||||||
|
resize(
|
||||||
|
shift_right(
|
||||||
|
m_axis_tdata_temp,
|
||||||
|
TRIANGULAR_COUNTER_LENGHT
|
||||||
|
),
|
||||||
|
CHANNEL_LENGHT
|
||||||
|
)
|
||||||
|
);
|
||||||
|
m_axis_tlast <= s_axis_tlast_reg;
|
||||||
|
|
||||||
|
m_axis_tvalid_int <= '1';
|
||||||
|
trigger <= '0';
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
-- Data input logic
|
||||||
|
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
|
||||||
IF lfo_enable = '1' THEN
|
IF lfo_enable = '1' THEN
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(
|
m_axis_tdata_temp <= signed(s_axis_tdata) * tri_counter;
|
||||||
resize(
|
s_axis_tlast_reg <= s_axis_tlast;
|
||||||
shift_right(
|
|
||||||
signed(s_axis_tdata) * tri_counter,
|
|
||||||
TRIANGULAR_COUNTER_LENGHT
|
|
||||||
),
|
|
||||||
CHANNEL_LENGHT
|
|
||||||
)
|
|
||||||
);
|
|
||||||
|
|
||||||
ELSE
|
ELSE
|
||||||
m_axis_tdata <= s_axis_tdata;
|
m_axis_tdata_temp <= shift_left(
|
||||||
|
resize(
|
||||||
|
signed(s_axis_tdata),
|
||||||
|
m_axis_tdata_temp'length
|
||||||
|
),
|
||||||
|
TRIANGULAR_COUNTER_LENGHT
|
||||||
|
);
|
||||||
|
s_axis_tlast_reg <= s_axis_tlast;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
m_axis_tvalid_int <= '1';
|
trigger <= '1';
|
||||||
m_axis_tlast <= s_axis_tlast;
|
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
|
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|||||||
@@ -24,6 +24,11 @@ END all_pass_filter;
|
|||||||
|
|
||||||
ARCHITECTURE Behavioral OF all_pass_filter IS
|
ARCHITECTURE Behavioral OF all_pass_filter IS
|
||||||
|
|
||||||
|
SIGNAL trigger : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
|
||||||
|
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
|
||||||
|
SIGNAL m_axis_tdata_temp : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
|
||||||
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
@@ -34,13 +39,19 @@ BEGIN
|
|||||||
|
|
||||||
-- Assigning the output signals
|
-- Assigning the output signals
|
||||||
m_axis_tvalid <= m_axis_tvalid_int;
|
m_axis_tvalid <= m_axis_tvalid_int;
|
||||||
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
|
s_axis_tready <= s_axis_tready_int;
|
||||||
|
|
||||||
PROCESS (aclk)
|
PROCESS (aclk)
|
||||||
BEGIN
|
BEGIN
|
||||||
IF rising_edge(aclk) THEN
|
IF rising_edge(aclk) THEN
|
||||||
|
|
||||||
IF aresetn = '0' THEN
|
IF aresetn = '0' THEN
|
||||||
|
-- Reset all internal signals
|
||||||
|
trigger <= '0';
|
||||||
|
|
||||||
|
s_axis_tlast_reg <= '0';
|
||||||
|
s_axis_tready_int <= '0';
|
||||||
|
m_axis_tdata_temp <= (OTHERS => '0');
|
||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
m_axis_tlast <= '0';
|
m_axis_tlast <= '0';
|
||||||
|
|
||||||
@@ -50,15 +61,27 @@ BEGIN
|
|||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
-- Handle data transfer
|
-- Data output logic
|
||||||
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
|
||||||
m_axis_tdata <= s_axis_tdata;
|
m_axis_tdata <= m_axis_tdata_temp;
|
||||||
|
m_axis_tlast <= s_axis_tlast_reg;
|
||||||
|
|
||||||
m_axis_tvalid_int <= '1';
|
m_axis_tvalid_int <= '1';
|
||||||
m_axis_tlast <= s_axis_tlast;
|
trigger <= '0';
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
|
-- Data input logic
|
||||||
|
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
|
||||||
|
s_axis_tlast_reg <= s_axis_tlast;
|
||||||
|
m_axis_tdata_temp <= s_axis_tdata;
|
||||||
|
|
||||||
|
trigger <= '1';
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|||||||
@@ -41,13 +41,19 @@ ARCHITECTURE Behavioral OF moving_average_filter IS
|
|||||||
SIGNAL sum_sx : signed(TDATA_WIDTH + FILTER_ORDER_POWER - 1 DOWNTO 0) := (OTHERS => '0');
|
SIGNAL sum_sx : signed(TDATA_WIDTH + FILTER_ORDER_POWER - 1 DOWNTO 0) := (OTHERS => '0');
|
||||||
SIGNAL wr_ptr_sx : INTEGER RANGE 0 TO FILTER_ORDER - 1 := 0;
|
SIGNAL wr_ptr_sx : INTEGER RANGE 0 TO FILTER_ORDER - 1 := 0;
|
||||||
|
|
||||||
|
-- Trigger signal to indicate when to output data
|
||||||
|
SIGNAL trigger : STD_LOGIC := '0';
|
||||||
|
|
||||||
|
-- Output signals
|
||||||
|
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
|
||||||
|
SIGNAL s_axis_tlast_reg : STD_LOGIC := '0';
|
||||||
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
|
|
||||||
-- Assigning the output signals
|
-- Assigning the output signals
|
||||||
m_axis_tvalid <= m_axis_tvalid_int;
|
m_axis_tvalid <= m_axis_tvalid_int;
|
||||||
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
|
s_axis_tready <= s_axis_tready_int;
|
||||||
|
|
||||||
PROCESS (aclk)
|
PROCESS (aclk)
|
||||||
BEGIN
|
BEGIN
|
||||||
@@ -62,6 +68,8 @@ BEGIN
|
|||||||
wr_ptr_dx <= 0;
|
wr_ptr_dx <= 0;
|
||||||
wr_ptr_sx <= 0;
|
wr_ptr_sx <= 0;
|
||||||
|
|
||||||
|
s_axis_tlast_reg <= '0';
|
||||||
|
s_axis_tready_int <= '0';
|
||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
m_axis_tlast <= '0';
|
m_axis_tlast <= '0';
|
||||||
|
|
||||||
@@ -71,10 +79,41 @@ BEGIN
|
|||||||
m_axis_tvalid_int <= '0';
|
m_axis_tvalid_int <= '0';
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
-- Get and process data
|
-- Data output logic
|
||||||
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
|
||||||
|
IF s_axis_tlast_reg = '1' THEN
|
||||||
|
m_axis_tdata <= STD_LOGIC_VECTOR(
|
||||||
|
resize(
|
||||||
|
shift_right(
|
||||||
|
sum_dx,
|
||||||
|
FILTER_ORDER_POWER
|
||||||
|
),
|
||||||
|
m_axis_tdata'length
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
IF s_axis_tlast = '1' THEN
|
ELSE
|
||||||
|
m_axis_tdata <= STD_LOGIC_VECTOR(
|
||||||
|
resize(
|
||||||
|
shift_right(
|
||||||
|
sum_sx,
|
||||||
|
FILTER_ORDER_POWER
|
||||||
|
),
|
||||||
|
m_axis_tdata'length
|
||||||
|
)
|
||||||
|
);
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
m_axis_tlast <= s_axis_tlast_reg;
|
||||||
|
|
||||||
|
m_axis_tvalid_int <= '1';
|
||||||
|
trigger <= '0';
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
-- Data input logic
|
||||||
|
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
|
||||||
|
IF s_axis_tlast = '1' THEN
|
||||||
-- Right channel
|
-- Right channel
|
||||||
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
|
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
|
||||||
samples_dx(wr_ptr_dx) <= signed(s_axis_tdata);
|
samples_dx(wr_ptr_dx) <= signed(s_axis_tdata);
|
||||||
@@ -85,16 +124,7 @@ BEGIN
|
|||||||
-- Update the sum_dx removing the oldest sample and adding the new one
|
-- Update the sum_dx removing the oldest sample and adding the new one
|
||||||
sum_dx <= sum_dx - samples_dx(wr_ptr_dx) + signed(s_axis_tdata);
|
sum_dx <= sum_dx - samples_dx(wr_ptr_dx) + signed(s_axis_tdata);
|
||||||
|
|
||||||
-- Calculate the average and send it to the master interface
|
s_axis_tlast_reg <= s_axis_tlast;
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(
|
|
||||||
resize(
|
|
||||||
shift_right(
|
|
||||||
sum_dx - samples_dx(wr_ptr_dx) + signed(s_axis_tdata),
|
|
||||||
FILTER_ORDER_POWER
|
|
||||||
),
|
|
||||||
m_axis_tdata'length
|
|
||||||
)
|
|
||||||
);
|
|
||||||
ELSE
|
ELSE
|
||||||
-- Left channel
|
-- Left channel
|
||||||
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
|
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
|
||||||
@@ -106,23 +136,15 @@ BEGIN
|
|||||||
-- Update the sum_dx removing the oldest sample and adding the new one
|
-- Update the sum_dx removing the oldest sample and adding the new one
|
||||||
sum_sx <= sum_sx - samples_sx(wr_ptr_sx) + signed(s_axis_tdata);
|
sum_sx <= sum_sx - samples_sx(wr_ptr_sx) + signed(s_axis_tdata);
|
||||||
|
|
||||||
-- Calculate the average and send it to the master interface
|
s_axis_tlast_reg <= s_axis_tlast;
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(
|
|
||||||
resize(
|
|
||||||
shift_right(
|
|
||||||
sum_sx - samples_sx(wr_ptr_sx) + signed(s_axis_tdata),
|
|
||||||
FILTER_ORDER_POWER
|
|
||||||
),
|
|
||||||
m_axis_tdata'length
|
|
||||||
)
|
|
||||||
);
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
m_axis_tvalid_int <= '1';
|
trigger <= '1';
|
||||||
m_axis_tlast <= s_axis_tlast;
|
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
|
s_axis_tready_int <= m_axis_tready OR NOT m_axis_tvalid_int;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|||||||
394
LAB3/vivado/LFO/LFO.xpr
Normal file
394
LAB3/vivado/LFO/LFO.xpr
Normal file
@@ -0,0 +1,394 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2020.2 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Version="7" Minor="54" Path="C:/DESD/LAB3/vivado/LFO/LFO.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="33adcfb9859e4aafa355a8ac0ff224f9"/>
|
||||||
|
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirIES" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||||
|
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="DSABoardId" Val="basys3"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="10"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../../src/LFO.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="LFO"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PPRDIR/../../sim/tb_LFO.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/tb_LFO_behav.wcfg">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tb_LFO"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_LFO_behav.wcfg"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="15">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="1"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||||
|
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="10"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="11"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val=""/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="12"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="2"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="3"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||||
|
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||||
|
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="4"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||||
|
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="5"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||||
|
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="6"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||||
|
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="7"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||||
|
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="8"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<MsgRule>
|
||||||
|
<MsgAttr Name="RuleType" Val="1"/>
|
||||||
|
<MsgAttr Name="Limit" Val="-1"/>
|
||||||
|
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||||
|
<MsgAttr Name="Id" Val="Synth 8-2490"/>
|
||||||
|
<MsgAttr Name="Severity" Val="ANY"/>
|
||||||
|
<MsgAttr Name="ShowRule" Val="1"/>
|
||||||
|
<MsgAttr Name="RuleSource" Val="2"/>
|
||||||
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||||
|
<MsgAttr Name="RuleId" Val="9"/>
|
||||||
|
<MsgAttr Name="Note" Val=""/>
|
||||||
|
<MsgAttr Name="Author" Val=""/>
|
||||||
|
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||||
|
</MsgRule>
|
||||||
|
<Board>
|
||||||
|
<Jumpers/>
|
||||||
|
</Board>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
104
LAB3/vivado/LFO/tb_LFO_behav.wcfg
Normal file
104
LAB3/vivado/LFO/tb_LFO_behav.wcfg
Normal file
@@ -0,0 +1,104 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<wave_config>
|
||||||
|
<wave_state>
|
||||||
|
</wave_state>
|
||||||
|
<db_ref_list>
|
||||||
|
<db_ref path="tb_LFO_behav.wdb" id="1">
|
||||||
|
<top_modules>
|
||||||
|
<top_module name="tb_LFO" />
|
||||||
|
</top_modules>
|
||||||
|
</db_ref>
|
||||||
|
</db_ref_list>
|
||||||
|
<zoom_setting>
|
||||||
|
<ZoomStartTime time="470972325000fs"></ZoomStartTime>
|
||||||
|
<ZoomEndTime time="483982325001fs"></ZoomEndTime>
|
||||||
|
<Cursor1Time time="475052325000fs"></Cursor1Time>
|
||||||
|
</zoom_setting>
|
||||||
|
<column_width_setting>
|
||||||
|
<NameColumnWidth column_width="147"></NameColumnWidth>
|
||||||
|
<ValueColumnWidth column_width="88"></ValueColumnWidth>
|
||||||
|
</column_width_setting>
|
||||||
|
<WVObjectSize size="17" />
|
||||||
|
<wvobject fp_name="/tb_LFO/aclk" type="logic">
|
||||||
|
<obj_property name="ElementShortName">aclk</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">aclk</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/aresetn" type="logic">
|
||||||
|
<obj_property name="ElementShortName">aresetn</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">aresetn</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/dut/step_counter" type="other">
|
||||||
|
<obj_property name="ElementShortName">step_counter</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">step_counter</obj_property>
|
||||||
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/dut/step_clk_cycles" type="other">
|
||||||
|
<obj_property name="ElementShortName">step_clk_cycles</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">step_clk_cycles</obj_property>
|
||||||
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/dut/tri_counter" type="array">
|
||||||
|
<obj_property name="ElementShortName">tri_counter[10:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">tri_counter[10:0]</obj_property>
|
||||||
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/lfo_period" type="array">
|
||||||
|
<obj_property name="ElementShortName">lfo_period[9:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">lfo_period[9:0]</obj_property>
|
||||||
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/lfo_enable" type="logic">
|
||||||
|
<obj_property name="ElementShortName">lfo_enable</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">lfo_enable</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider36">
|
||||||
|
<obj_property name="label">s_axis</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/s_axis_tdata" type="array">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/s_axis_tlast" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/s_axis_tvalid" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/s_axis_tready" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider35">
|
||||||
|
<obj_property name="label">m_axis</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/m_axis_tdata" type="array">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/m_axis_tlast" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/m_axis_tvalid" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_LFO/m_axis_tready" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tready</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wave_config>
|
||||||
@@ -89,42 +89,12 @@
|
|||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/led_controller.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../src/mute_controller.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
|
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../src/moving_average_filter.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<File Path="$PPRDIR/../../src/volume_multiplier.vhd">
|
<File Path="$PPRDIR/../../src/volume_multiplier.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
@@ -155,13 +125,43 @@
|
|||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/LFO.vhd">
|
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
|
<File Path="$PPRDIR/../../src/led_controller.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/../../src/moving_average_filter.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/../../src/mute_controller.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/../../src/LFO.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
|||||||
@@ -47,7 +47,7 @@
|
|||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
<Option Name="EnableBDX" Val="FALSE"/>
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
<Option Name="DSABoardId" Val="basys3"/>
|
<Option Name="DSABoardId" Val="basys3"/>
|
||||||
<Option Name="WTXSimLaunchSim" Val="11"/>
|
<Option Name="WTXSimLaunchSim" Val="18"/>
|
||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
@@ -107,6 +107,7 @@
|
|||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
<File Path="$PPRDIR/../../sim/tb_moving_average.vhd">
|
<File Path="$PPRDIR/../../sim/tb_moving_average.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
@@ -162,9 +163,7 @@
|
|||||||
<Runs Version="1" Minor="15">
|
<Runs Version="1" Minor="15">
|
||||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||||
<Desc>Vivado Synthesis Defaults</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="synth_design"/>
|
<Step Id="synth_design"/>
|
||||||
</Strategy>
|
</Strategy>
|
||||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||||
@@ -173,9 +172,7 @@
|
|||||||
</Run>
|
</Run>
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||||
<Desc>Default settings for Implementation.</Desc>
|
|
||||||
</StratHandle>
|
|
||||||
<Step Id="init_design"/>
|
<Step Id="init_design"/>
|
||||||
<Step Id="opt_design"/>
|
<Step Id="opt_design"/>
|
||||||
<Step Id="power_opt_design"/>
|
<Step Id="power_opt_design"/>
|
||||||
|
|||||||
@@ -11,14 +11,14 @@
|
|||||||
</db_ref_list>
|
</db_ref_list>
|
||||||
<zoom_setting>
|
<zoom_setting>
|
||||||
<ZoomStartTime time="0fs"></ZoomStartTime>
|
<ZoomStartTime time="0fs"></ZoomStartTime>
|
||||||
<ZoomEndTime time="648001fs"></ZoomEndTime>
|
<ZoomEndTime time="260201fs"></ZoomEndTime>
|
||||||
<Cursor1Time time="195000fs"></Cursor1Time>
|
<Cursor1Time time="0fs"></Cursor1Time>
|
||||||
</zoom_setting>
|
</zoom_setting>
|
||||||
<column_width_setting>
|
<column_width_setting>
|
||||||
<NameColumnWidth column_width="147"></NameColumnWidth>
|
<NameColumnWidth column_width="147"></NameColumnWidth>
|
||||||
<ValueColumnWidth column_width="93"></ValueColumnWidth>
|
<ValueColumnWidth column_width="88"></ValueColumnWidth>
|
||||||
</column_width_setting>
|
</column_width_setting>
|
||||||
<WVObjectSize size="13" />
|
<WVObjectSize size="18" />
|
||||||
<wvobject fp_name="/tb_moving_average/aclk" type="logic">
|
<wvobject fp_name="/tb_moving_average/aclk" type="logic">
|
||||||
<obj_property name="ElementShortName">aclk</obj_property>
|
<obj_property name="ElementShortName">aclk</obj_property>
|
||||||
<obj_property name="ObjectShortName">aclk</obj_property>
|
<obj_property name="ObjectShortName">aclk</obj_property>
|
||||||
@@ -83,4 +83,26 @@
|
|||||||
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
</wvobject>
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider18">
|
||||||
|
<obj_property name="label">moving average</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_moving_average/dut/moving_avg_inst/sum_dx" type="array">
|
||||||
|
<obj_property name="ElementShortName">sum_dx[28:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">sum_dx[28:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_moving_average/dut/moving_avg_inst/sum_sx" type="array">
|
||||||
|
<obj_property name="ElementShortName">sum_sx[28:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">sum_sx[28:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_moving_average/dut/moving_avg_inst/wr_ptr_dx" type="other">
|
||||||
|
<obj_property name="ElementShortName">wr_ptr_dx</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">wr_ptr_dx</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_moving_average/dut/moving_avg_inst/wr_ptr_sx" type="other">
|
||||||
|
<obj_property name="ElementShortName">wr_ptr_sx</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">wr_ptr_sx</obj_property>
|
||||||
|
</wvobject>
|
||||||
</wave_config>
|
</wave_config>
|
||||||
|
|||||||
Reference in New Issue
Block a user