diff --git a/.gitignore b/.gitignore
index 58ea3db..73b2a23 100644
--- a/.gitignore
+++ b/.gitignore
@@ -82,6 +82,6 @@ vivado*.backup.log
 # Other files
 **/test/*.zip
 **/test/*.exe
-**/test/*.spec
-**/test/dist/
-**/test/build/
\ No newline at end of file
+*.spec
+**/dist/
+**/build/
\ No newline at end of file
diff --git a/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
index 7c5fa58..726d18d 100644
--- a/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
+++ b/LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
@@ -1,7 +1,7 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Fri May 30 13:53:25 2025
+--Date        : Fri May 30 14:28:09 2025
 --Host        : DavideASUS running 64-bit major release  (build 9200)
 --Command     : generate_target lab_3_wrapper.bd
 --Design      : lab_3_wrapper
diff --git a/LAB3/design/lab_3/lab_3.bd b/LAB3/design/lab_3/lab_3.bd
index 194a1fe..9863b6c 100644
--- a/LAB3/design/lab_3/lab_3.bd
+++ b/LAB3/design/lab_3/lab_3.bd
@@ -25,9 +25,9 @@
       "led_level_controller_0": "",
       "led_controller_0": "",
       "mute_controller_0": "",
-      "digilent_jstk2_0": "",
       "moving_average_filte_0": "",
-      "LFO_0": ""
+      "LFO_0": "",
+      "digilent_jstk2_0": ""
     },
     "interface_ports": {
       "SPI_M_0": {
@@ -1191,221 +1191,6 @@
           }
         }
       },
-      "digilent_jstk2_0": {
-        "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
-        "xci_name": "lab_3_digilent_jstk2_0_0",
-        "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
-        "inst_hier_path": "digilent_jstk2_0",
-        "parameters": {
-          "CLKFREQ": {
-            "value": "215000000"
-          }
-        },
-        "reference_info": {
-          "ref_type": "hdl",
-          "ref_name": "digilent_jstk2",
-          "boundary_crc": "0x0"
-        },
-        "interface_ports": {
-          "m_axis": {
-            "mode": "Master",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "m_axis_tdata",
-                "direction": "O",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "m_axis_tvalid",
-                "direction": "O"
-              },
-              "TREADY": {
-                "physical_name": "m_axis_tready",
-                "direction": "I"
-              }
-            }
-          },
-          "s_axis": {
-            "mode": "Slave",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "s_axis_tdata",
-                "direction": "I",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "s_axis_tvalid",
-                "direction": "I"
-              }
-            }
-          }
-        },
-        "ports": {
-          "aclk": {
-            "type": "clk",
-            "direction": "I",
-            "parameters": {
-              "ASSOCIATED_BUSIF": {
-                "value": "m_axis:s_axis",
-                "value_src": "constant"
-              },
-              "ASSOCIATED_RESET": {
-                "value": "aresetn",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            }
-          },
-          "aresetn": {
-            "type": "rst",
-            "direction": "I",
-            "parameters": {
-              "POLARITY": {
-                "value": "ACTIVE_LOW",
-                "value_src": "constant"
-              }
-            }
-          },
-          "jstk_x": {
-            "direction": "O",
-            "left": "9",
-            "right": "0"
-          },
-          "jstk_y": {
-            "direction": "O",
-            "left": "9",
-            "right": "0"
-          },
-          "btn_jstk": {
-            "direction": "O"
-          },
-          "btn_trigger": {
-            "direction": "O"
-          },
-          "led_r": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          },
-          "led_g": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          },
-          "led_b": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          }
-        }
-      },
       "moving_average_filte_0": {
         "vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
         "xci_name": "lab_3_moving_average_filte_0_0",
@@ -1803,74 +1588,289 @@
             "direction": "I"
           }
         }
+      },
+      "digilent_jstk2_0": {
+        "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
+        "xci_name": "lab_3_digilent_jstk2_0_0",
+        "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
+        "inst_hier_path": "digilent_jstk2_0",
+        "parameters": {
+          "CLKFREQ": {
+            "value": "215000000"
+          }
+        },
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "digilent_jstk2",
+          "boundary_crc": "0x0"
+        },
+        "interface_ports": {
+          "m_axis": {
+            "mode": "Master",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "m_axis_tdata",
+                "direction": "O",
+                "left": "7",
+                "right": "0"
+              },
+              "TVALID": {
+                "physical_name": "m_axis_tvalid",
+                "direction": "O"
+              },
+              "TREADY": {
+                "physical_name": "m_axis_tready",
+                "direction": "I"
+              }
+            }
+          },
+          "s_axis": {
+            "mode": "Slave",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "s_axis_tdata",
+                "direction": "I",
+                "left": "7",
+                "right": "0"
+              },
+              "TVALID": {
+                "physical_name": "s_axis_tvalid",
+                "direction": "I"
+              }
+            }
+          }
+        },
+        "ports": {
+          "aclk": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "ASSOCIATED_BUSIF": {
+                "value": "m_axis:s_axis",
+                "value_src": "constant"
+              },
+              "ASSOCIATED_RESET": {
+                "value": "aresetn",
+                "value_src": "constant"
+              },
+              "FREQ_HZ": {
+                "value": "100000000",
+                "value_src": "ip_prop"
+              },
+              "PHASE": {
+                "value": "0.0",
+                "value_src": "ip_prop"
+              },
+              "CLK_DOMAIN": {
+                "value": "/clk_wiz_0_clk_out1",
+                "value_src": "ip_prop"
+              }
+            }
+          },
+          "aresetn": {
+            "type": "rst",
+            "direction": "I",
+            "parameters": {
+              "POLARITY": {
+                "value": "ACTIVE_LOW",
+                "value_src": "constant"
+              }
+            }
+          },
+          "jstk_x": {
+            "direction": "O",
+            "left": "9",
+            "right": "0"
+          },
+          "jstk_y": {
+            "direction": "O",
+            "left": "9",
+            "right": "0"
+          },
+          "btn_jstk": {
+            "direction": "O"
+          },
+          "btn_trigger": {
+            "direction": "O"
+          },
+          "led_r": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "led_g": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "led_b": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          }
+        }
       }
     },
     "interface_nets": {
-      "axis_dual_i2s_0_m_axis": {
-        "interface_ports": [
-          "axis_dual_i2s_0/m_axis",
-          "moving_average_filte_0/s_axis"
-        ]
-      },
-      "moving_average_filte_0_m_axis": {
-        "interface_ports": [
-          "balance_controller_0/s_axis",
-          "moving_average_filte_0/m_axis"
-        ]
-      },
-      "balance_controller_0_m_axis": {
-        "interface_ports": [
-          "balance_controller_0/m_axis",
-          "volume_controller_0/s_axis"
-        ]
-      },
-      "digilent_jstk2_0_m_axis": {
-        "interface_ports": [
-          "digilent_jstk2_0/m_axis",
-          "axi4stream_spi_master_0/S_AXIS"
-        ]
-      },
-      "axis_broadcaster_0_M00_AXIS": {
-        "interface_ports": [
-          "axis_broadcaster_0/M00_AXIS",
-          "axis_dual_i2s_0/s_axis"
-        ]
-      },
       "volume_controller_0_m_axis": {
         "interface_ports": [
           "volume_controller_0/m_axis",
           "LFO_0/s_axis"
         ]
       },
-      "axis_broadcaster_0_M01_AXIS": {
-        "interface_ports": [
-          "axis_broadcaster_0/M01_AXIS",
-          "led_level_controller_0/s_axis"
-        ]
-      },
-      "axi4stream_spi_master_0_M_AXIS": {
-        "interface_ports": [
-          "axi4stream_spi_master_0/M_AXIS",
-          "digilent_jstk2_0/s_axis"
-        ]
-      },
-      "LFO_0_m_axis": {
-        "interface_ports": [
-          "LFO_0/m_axis",
-          "mute_controller_0/s_axis"
-        ]
-      },
       "mute_controller_0_m_axis": {
         "interface_ports": [
           "mute_controller_0/m_axis",
           "axis_broadcaster_0/S_AXIS"
         ]
       },
+      "moving_average_filte_0_m_axis": {
+        "interface_ports": [
+          "balance_controller_0/s_axis",
+          "moving_average_filte_0/m_axis"
+        ]
+      },
+      "axis_dual_i2s_0_m_axis": {
+        "interface_ports": [
+          "axis_dual_i2s_0/m_axis",
+          "moving_average_filte_0/s_axis"
+        ]
+      },
+      "digilent_jstk2_0_m_axis": {
+        "interface_ports": [
+          "digilent_jstk2_0/m_axis",
+          "axi4stream_spi_master_0/S_AXIS"
+        ]
+      },
+      "LFO_0_m_axis": {
+        "interface_ports": [
+          "LFO_0/m_axis",
+          "mute_controller_0/s_axis"
+        ]
+      },
       "axi4stream_spi_master_0_SPI_M": {
         "interface_ports": [
           "SPI_M_0",
           "axi4stream_spi_master_0/SPI_M"
         ]
+      },
+      "axis_broadcaster_0_M00_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_0/M00_AXIS",
+          "axis_dual_i2s_0/s_axis"
+        ]
+      },
+      "axis_broadcaster_0_M01_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_0/M01_AXIS",
+          "led_level_controller_0/s_axis"
+        ]
+      },
+      "balance_controller_0_m_axis": {
+        "interface_ports": [
+          "balance_controller_0/m_axis",
+          "volume_controller_0/s_axis"
+        ]
+      },
+      "axi4stream_spi_master_0_M_AXIS": {
+        "interface_ports": [
+          "axi4stream_spi_master_0/M_AXIS",
+          "digilent_jstk2_0/s_axis"
+        ]
       }
     },
     "nets": {
@@ -1895,9 +1895,9 @@
           "effect_selector_0/aclk",
           "led_level_controller_0/aclk",
           "mute_controller_0/aclk",
-          "digilent_jstk2_0/aclk",
           "moving_average_filte_0/aclk",
-          "LFO_0/aclk"
+          "LFO_0/aclk",
+          "digilent_jstk2_0/aclk"
         ]
       },
       "reset_1": {
@@ -1934,9 +1934,9 @@
           "effect_selector_0/aresetn",
           "led_level_controller_0/aresetn",
           "mute_controller_0/aresetn",
-          "digilent_jstk2_0/aresetn",
           "moving_average_filte_0/aresetn",
-          "LFO_0/aresetn"
+          "LFO_0/aresetn",
+          "digilent_jstk2_0/aresetn"
         ]
       },
       "proc_sys_reset_1_peripheral_aresetn": {
diff --git a/LAB3/design/lab_3/lab_3.bda b/LAB3/design/lab_3/lab_3.bda
index 83f8ab8..c595aff 100644
--- a/LAB3/design/lab_3/lab_3.bda
+++ b/LAB3/design/lab_3/lab_3.bda
@@ -21,22 +21,22 @@
   <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
   <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
     <node id="n0">
-      <data key="TU">active</data>
-      <data key="VH">2</data>
-      <data key="VT">PM</data>
-    </node>
-    <node id="n1">
       <data key="VH">2</data>
       <data key="VM">lab_3</data>
       <data key="VT">VR</data>
     </node>
-    <node id="n2">
+    <node id="n1">
       <data key="VM">lab_3</data>
       <data key="VT">BC</data>
     </node>
-    <edge id="e0" source="n2" target="n1">
+    <node id="n2">
+      <data key="TU">active</data>
+      <data key="VH">2</data>
+      <data key="VT">PM</data>
+    </node>
+    <edge id="e0" source="n1" target="n0">
     </edge>
-    <edge id="e1" source="n1" target="n0">
+    <edge id="e1" source="n0" target="n2">
     </edge>
   </graph>
 </graphml>
diff --git a/LAB3/src/digilent_jstk2.vhd b/LAB3/src/digilent_jstk2.vhd
index 4552fc7..418ac61 100644
--- a/LAB3/src/digilent_jstk2.vhd
+++ b/LAB3/src/digilent_jstk2.vhd
@@ -46,7 +46,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
     -- Uses integer arithmetic optimized to avoid truncation by performing multiplications before divisions
     -- Formula: ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000)
     -- This ensures proper timing between SPI packets as required by JSTK2 datasheet
-    CONSTANT DELAY_CLK_CYCLES : INTEGER := ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000);
+    CONSTANT DELAY_CLK_CYCLES : INTEGER := ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000) + 1;
 
     -- State machine type definitions
     TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
@@ -57,8 +57,8 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
     SIGNAL rx_state : rx_state_type := JSTK_X_LOW;      -- Receive state machine current state
 
     -- Timing and data storage signals
-    SIGNAL tx_delay_counter : INTEGER := 0;             -- Counter for inter-packet delay timing
-    SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);     -- Temporary storage for multi-byte data reception
+    SIGNAL tx_delay_counter : INTEGER RANGE 0 TO DELAY_CLK_CYCLES := 0;  -- Counter for inter-packet delay timing
+    SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);                      -- Temporary storage for multi-byte data reception
 
 BEGIN
 
@@ -97,7 +97,7 @@ BEGIN
 
                     WHEN DELAY =>
                         -- Wait for required delay period between SPI transactions
-                        IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
+                        IF tx_delay_counter = DELAY_CLK_CYCLES THEN
                             tx_delay_counter <= 0;     -- Reset counter
                             tx_state <= SEND_CMD;      -- Start new transmission
                         ELSE