- update comments
- add led_level_controller Const
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@@ -16,17 +16,17 @@ ENTITY digilent_jstk2 IS
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-- AXI4-Stream Master Interface: Data going TO the SPI IP-Core (and so, to the JSTK2 module)
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m_axis_tvalid : OUT STD_LOGIC; -- Output data valid signal
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit data to send via SPI
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit data to send via SPI
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m_axis_tready : IN STD_LOGIC; -- SPI IP-Core ready to accept data
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-- AXI4-Stream Slave Interface: Data coming FROM the SPI IP-Core (and so, from the JSTK2 module)
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-- Note: There is no tready signal, so you must be always ready to accept incoming data, or it will be lost!
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s_axis_tvalid : IN STD_LOGIC; -- Input data valid signal
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit data received via SPI
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 8-bit data received via SPI
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-- Joystick and button values read from the JSTK2 module
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jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- X-axis joystick position (10-bit, 0-1023)
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jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- Y-axis joystick position (10-bit, 0-1023)
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jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- X-axis joystick position (10-bit, 0-1023)
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jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); -- Y-axis joystick position (10-bit, 0-1023)
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btn_jstk : OUT STD_LOGIC; -- Joystick button state (1=pressed)
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btn_trigger : OUT STD_LOGIC; -- Trigger button state (1=pressed)
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@@ -44,7 +44,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
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-- Calculate delay in clock cycles: (delay_period + 1_SPI_clock_period) * clock_frequency
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-- This ensures proper timing between SPI packets as required by JSTK2 datasheet
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CONSTANT DELAY_CLK_CYCLES : INTEGER := (DELAY_US + 1_000_000 / SPI_SCLKFREQ) * (CLKFREQ / 1_000_000);
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CONSTANT DELAY_CLK_CYCLES : INTEGER := (DELAY_US + 1_000_000 / SPI_SCLKFREQ) * (CLKFREQ / 1_000_000) - 1;
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-- State machine type definitions
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TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
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@@ -56,7 +56,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
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-- Timing and data storage signals
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SIGNAL tx_delay_counter : INTEGER RANGE 0 TO DELAY_CLK_CYCLES := 0; -- Counter for inter-packet delay timing
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SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Temporary storage for multi-byte data reception
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SIGNAL rx_cache : STD_LOGIC_VECTOR(s_axis_tdata'range); -- Temporary storage for multi-byte data reception
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BEGIN
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@@ -80,7 +80,8 @@ BEGIN
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"01101001" WHEN SEND_DUMMY; -- Dummy byte to complete 5-byte transaction
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-- TX State Machine: Sends LED color commands to JSTK2 module
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-- Protocol: Command(1) + Red(1) + Green(1) + Blue(1) + Dummy(1) = 5 bytes total
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-- Protocol: Command(1) + Red(1) + Green(1) + Blue(1) + Dummy(1) = 5 bytes total > Delay before next command
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-- The delay is required by the JSTK datasheet to ensure proper timing between SPI transactions
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TX : PROCESS (aclk)
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BEGIN
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IF rising_edge(aclk) THEN
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