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Refactor and clean up project files

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- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.
This commit is contained in:
Davide Cavagnola
2025-04-22 22:32:01 +02:00
parent e2bcbf7d31
commit f014f8c341
42 changed files with 747 additions and 19051 deletions
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81
LAB2/src/rgb2gray.vhd
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@@ -1,13 +1,6 @@
---------- DEFAULT LIBRARIES -------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL; -- For logarithmic calculations (used for a constant)
------------------------------------
---------- OTHER LIBRARIES ---------
-- NONE
------------------------------------
ENTITY rgb2gray IS
PORT (
@@ -34,19 +27,30 @@ ARCHITECTURE Behavioral OF rgb2gray IS
);
PORT (
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0));
END COMPONENT divider_by_3;
result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
);
END COMPONENT;
TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B);
SIGNAL state : state_type := WAIT_R;
SIGNAL r_val, g_val : unsigned(7 DOWNTO 0);
SIGNAL sum : unsigned(8 DOWNTO 0);
SIGNAL r_val, g_val : UNSIGNED(7 DOWNTO 0);
SIGNAL sum : UNSIGNED(8 DOWNTO 0);
SIGNAL gray : UNSIGNED(6 DOWNTO 0);
SIGNAL send_data : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tready_int : STD_LOGIC := '1';
BEGIN
-- Port mappings
m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
s_axis_tready <= s_axis_tready_int;
-- Divider instance
DIVIDER : divider_by_3
GENERIC MAP(
BIT_DEPTH => 7
@@ -62,55 +66,58 @@ BEGIN
IF resetn = '0' THEN
-- Reset all signals
state <= WAIT_R;
s_axis_tready <= '1';
m_axis_tvalid <= '0';
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tdata_int <= (OTHERS => '0');
r_val <= (OTHERS => '0');
g_val <= (OTHERS => '0');
sum <= (OTHERS => '0');
ELSE
-- Default control signals
m_axis_tlast <= s_axis_tlast;
m_axis_tvalid <= '0';
send_data <= '0';
-- If downstream is ready, send the grayscale pixel
IF m_axis_tready = '1' AND send_data = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR('0' & gray);
m_axis_tvalid <= '1';
ELSE
-- Propagate TLAST
m_axis_tlast <= s_axis_tlast;
-- Clear valid once data has been accepted
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
-- Issue new output only when back?pressure is released
IF send_data = '1' AND m_axis_tready = '1' THEN
m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray); -- MSB zero + 7?bit gray
m_axis_tvalid_int <= '1';
send_data <= '0';
END IF;
-- Back?pressure: blocca ingresso finch<63> non hai trasmesso
IF send_data = '1' OR (m_axis_tvalid_int = '1' AND m_axis_tready = '0') THEN
s_axis_tready_int <= '0';
ELSE
s_axis_tready_int <= '1';
END IF;
-- FSM per ricezione R, G, B
CASE state IS
WHEN WAIT_R =>
IF s_axis_tvalid = '1' THEN
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
r_val <= unsigned(s_axis_tdata);
IF m_axis_tready = '0' THEN
s_axis_tready <= '0';
END IF;
state <= WAIT_G;
END IF;
WHEN WAIT_G =>
IF s_axis_tvalid = '1' THEN
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
g_val <= unsigned(s_axis_tdata);
IF m_axis_tready = '1' THEN
s_axis_tready <= '1';
state <= WAIT_B;
END IF;
state <= WAIT_B;
END IF;
WHEN WAIT_B =>
IF s_axis_tvalid = '1' THEN
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= RESIZE(r_val + g_val + unsigned(s_axis_tdata), 9);
send_data <= '1';
state <= WAIT_R;
END IF;
END CASE;
END IF;
END IF;