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Refactor KittCarPWM logic for improved LED direction handling and clean up Vivado project settings

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This commit is contained in:
Davide Cavagnola
2025-03-21 17:47:28 +01:00
parent 038ea73291
commit f6c568b416
2 changed files with 16 additions and 18 deletions
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25
LAB1/src/KittCarPWM.vhd
View File

@@ -86,12 +86,13 @@ BEGIN
leds_sr <= (OTHERS => 0);
led_sig <= (OTHERS => '0');
counter := (OTHERS => '0');
up <= '1';
ELSIF rising_edge(clk) THEN
-- Kitt logic
IF leds_sr(TAIL_LENGTH - 1) = 15 THEN
-- Kitt logic: Update direction
IF leds_sr(TAIL_LENGTH - 1) = led'high THEN
up <= '0';
ELSIF leds_sr(TAIL_LENGTH - 1) = 0 THEN
ELSIF leds_sr(TAIL_LENGTH - 1) = led'low THEN
up <= '1';
END IF;
@@ -101,17 +102,17 @@ BEGIN
-- Calculate the number of periods
IF counter >= (MIN_KITT_CAR_STEP_NS * n_period) THEN
-- Shift the leds
IF up = '1' THEN
leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
ELSIF up = '0' THEN
leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 2 DOWNTO 0);
END IF;
-- Reset leg_sig
-- Reset led_sig
led_sig <= (OTHERS => '0');
-- Assign the leds
-- Shift the leds
IF up = '1' THEN
leds_sr <= (leds_sr(TAIL_LENGTH - 1) + 1) & leds_sr(TAIL_LENGTH - 1 DOWNTO 1);
ELSE
leds_sr <= (leds_sr(TAIL_LENGTH - 1) - 1) & leds_sr(TAIL_LENGTH - 1 DOWNTO 1);
END IF;
-- Assign the LEDs
FOR i IN 0 TO TAIL_LENGTH - 1 LOOP
led_sig(leds_sr(i)) <= leds_pwm(i);
END LOOP;

9
LAB1/vivado/lab1_kit_car_pwm/lab1_kit_car_pwm.xpr
View File

@@ -106,6 +106,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="KittCarPWM"/>
@@ -149,9 +150,7 @@
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -161,9 +160,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>