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compare: PickleRick:d65bb35afe39fa5f91939410993a6d46dc2a8c54
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PickleRick:main

2 Commits
e21c00512f ... d65bb35afe

Author SHA1 Message Date
Davide
d65bb35afe Update .gitignore, lab_3_wrapper.vhd, lab_3.bd, lab_3.bda, and digilent_jstk2.vhd for improved organization and functionality 2025-05-30 14:32:33 +02:00
Davide
d156d1c944 Refactor project structure and update dependencies 
- Updated .gitignore to exclude virtual environment and additional test files.
- Modified diligent_jstk.bd to reorganize interface nets for clarity.
- Adjusted diligent_jstk.bda to correct node attributes and edges.
- Revised diligent_jstk_wrapper.vhd to ensure proper port declarations.
- Enhanced uart_viewer.py for improved image handling and serial connection checks.
- Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations.
- Added requirements.txt to specify project dependencies for Python packages.
 2025-05-30 14:14:25 +02:00
12 changed files with 471 additions and 401 deletions
Expand all files Collapse all files

7
.gitignore vendored
View File

@@ -45,7 +45,6 @@
*.bxml
*.zip
# Vivado project directories
*.sim/
*.cache/
@@ -65,6 +64,8 @@ vivado_pid*.str
vivado*.backup.jou
vivado*.backup.log
# Directories to ignore
.venv
# SDK workspace
.sdk/
@@ -80,3 +81,7 @@ vivado*.backup.log
# Other files
**/test/*.zip
**/test/*.exe
*.spec
**/dist/
**/build/

26
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -591,13 +591,6 @@
}
},
"interface_nets": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
@@ -610,10 +603,17 @@
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_UART": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"digilent_jstk2_0_m_axis": {
@@ -623,10 +623,10 @@
"system_ila_0/SLOT_0_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
"usb_uart",
"AXI4Stream_UART_0/UART"
]
}
},

22
LAB3/design/diligent_jstk/diligent_jstk.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n0" target="n2">
<node id="n1">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n2" target="n1">
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>

10
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 19 09:11:39 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Date : Fri May 30 13:56:20 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
--Purpose : IP block netlist
@@ -29,8 +29,6 @@ architecture STRUCTURE of diligent_jstk_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
@@ -42,7 +40,9 @@ architecture STRUCTURE of diligent_jstk_wrapper is
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC
SPI_M_0_io0_i : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component diligent_jstk;
component IOBUF is

2
LAB3/design/lab_3/hdl/lab_3_wrapper.vhd
View File

@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri May 30 13:53:25 2025
--Date : Fri May 30 14:28:09 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_3_wrapper.bd
--Design : lab_3_wrapper

538
LAB3/design/lab_3/lab_3.bd
View File

@@ -25,9 +25,9 @@
"led_level_controller_0": "",
"led_controller_0": "",
"mute_controller_0": "",
"digilent_jstk2_0": "",
"moving_average_filte_0": "",
"LFO_0": ""
"LFO_0": "",
"digilent_jstk2_0": ""
},
"interface_ports": {
"SPI_M_0": {
@@ -1191,221 +1191,6 @@
}
}
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "lab_3_digilent_jstk2_0_0",
"xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"CLKFREQ": {
"value": "215000000"
}
},
"reference_info": {
"ref_type": "hdl",
"ref_name": "digilent_jstk2",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "0",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "O",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "O",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "O"
},
"btn_trigger": {
"direction": "O"
},
"led_r": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "I",
"left": "7",
"right": "0"
}
}
},
"moving_average_filte_0": {
"vlnv": "xilinx.com:module_ref:moving_average_filter_en:1.0",
"xci_name": "lab_3_moving_average_filte_0_0",
@@ -1803,74 +1588,289 @@
"direction": "I"
}
}
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "lab_3_digilent_jstk2_0_0",
"xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"parameters": {
"CLKFREQ": {
"value": "215000000"
}
},
"reference_info": {
"ref_type": "hdl",
"ref_name": "digilent_jstk2",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "0",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "O",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "O",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "O"
},
"btn_trigger": {
"direction": "O"
},
"led_r": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "I",
"left": "7",
"right": "0"
}
}
}
},
"interface_nets": {
"axis_dual_i2s_0_m_axis": {
"interface_ports": [
"axis_dual_i2s_0/m_axis",
"moving_average_filte_0/s_axis"
]
},
"moving_average_filte_0_m_axis": {
"interface_ports": [
"balance_controller_0/s_axis",
"moving_average_filte_0/m_axis"
]
},
"balance_controller_0_m_axis": {
"interface_ports": [
"balance_controller_0/m_axis",
"volume_controller_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS"
]
},
"axis_broadcaster_0_M00_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M00_AXIS",
"axis_dual_i2s_0/s_axis"
]
},
"volume_controller_0_m_axis": {
"interface_ports": [
"volume_controller_0/m_axis",
"LFO_0/s_axis"
]
},
"axis_broadcaster_0_M01_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M01_AXIS",
"led_level_controller_0/s_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis"
]
},
"LFO_0_m_axis": {
"interface_ports": [
"LFO_0/m_axis",
"mute_controller_0/s_axis"
]
},
"mute_controller_0_m_axis": {
"interface_ports": [
"mute_controller_0/m_axis",
"axis_broadcaster_0/S_AXIS"
]
},
"moving_average_filte_0_m_axis": {
"interface_ports": [
"balance_controller_0/s_axis",
"moving_average_filte_0/m_axis"
]
},
"axis_dual_i2s_0_m_axis": {
"interface_ports": [
"axis_dual_i2s_0/m_axis",
"moving_average_filte_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS"
]
},
"LFO_0_m_axis": {
"interface_ports": [
"LFO_0/m_axis",
"mute_controller_0/s_axis"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"axis_broadcaster_0_M00_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M00_AXIS",
"axis_dual_i2s_0/s_axis"
]
},
"axis_broadcaster_0_M01_AXIS": {
"interface_ports": [
"axis_broadcaster_0/M01_AXIS",
"led_level_controller_0/s_axis"
]
},
"balance_controller_0_m_axis": {
"interface_ports": [
"balance_controller_0/m_axis",
"volume_controller_0/s_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis"
]
}
},
"nets": {
@@ -1895,9 +1895,9 @@
"effect_selector_0/aclk",
"led_level_controller_0/aclk",
"mute_controller_0/aclk",
"digilent_jstk2_0/aclk",
"moving_average_filte_0/aclk",
"LFO_0/aclk"
"LFO_0/aclk",
"digilent_jstk2_0/aclk"
]
},
"reset_1": {
@@ -1934,9 +1934,9 @@
"effect_selector_0/aresetn",
"led_level_controller_0/aresetn",
"mute_controller_0/aresetn",
"digilent_jstk2_0/aresetn",
"moving_average_filte_0/aresetn",
"LFO_0/aresetn"
"LFO_0/aresetn",
"digilent_jstk2_0/aresetn"
]
},
"proc_sys_reset_1_peripheral_aresetn": {

16
LAB3/design/lab_3/lab_3.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">lab_3</data>
<data key="VT">VR</data>
</node>
<node id="n2">
<node id="n1">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n1">
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n1" target="n0">
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>

6
LAB3/src/digilent_jstk2.vhd
View File

@@ -46,7 +46,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
-- Uses integer arithmetic optimized to avoid truncation by performing multiplications before divisions
-- Formula: ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000)
-- This ensures proper timing between SPI packets as required by JSTK2 datasheet
CONSTANT DELAY_CLK_CYCLES : INTEGER := ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000);
CONSTANT DELAY_CLK_CYCLES : INTEGER := ((DELAY_US * SPI_SCLKFREQ + 1_000_000) * CLKFREQ) / (SPI_SCLKFREQ * 1_000_000) + 1;
-- State machine type definitions
TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
@@ -57,7 +57,7 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
SIGNAL rx_state : rx_state_type := JSTK_X_LOW; -- Receive state machine current state
-- Timing and data storage signals
SIGNAL tx_delay_counter : INTEGER := 0; -- Counter for inter-packet delay timing
SIGNAL tx_delay_counter : INTEGER RANGE 0 TO DELAY_CLK_CYCLES := 0; -- Counter for inter-packet delay timing
SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0); -- Temporary storage for multi-byte data reception
BEGIN
@@ -97,7 +97,7 @@ BEGIN
WHEN DELAY =>
-- Wait for required delay period between SPI transactions
IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
IF tx_delay_counter = DELAY_CLK_CYCLES THEN
tx_delay_counter <= 0; -- Reset counter
tx_state <= SEND_CMD; -- Start new transmission
ELSE

7
LAB3/test/uart_viewer.py
View File

@@ -63,11 +63,11 @@ def receive_graph_mode(ser):
# Load PNG directly
png_path = r'LAB3\test\Color_circle_(RGB).png'
img = Image.open(png_path).convert('RGB')
img = img.resize((127, 127), Image.LANCZOS) # Ensure image is 127x127
img = img.resize((127, 127), Image.Resampling.LANCZOS) # Ensure image is 127x127
img_np = np.array(img)
# Show the image as background
ax.imshow(img, extent=[0, 127, 0, 127], aspect='auto', zorder=0)
ax.imshow(img, extent=(0, 127, 0, 127), aspect='auto', zorder=0)
sc = ax.scatter([point[0]], [point[1]], s=[size], zorder=1)
ax.set_xlim(0, 127)
@@ -146,6 +146,7 @@ def send_mode(ser):
print("\nChiusura modalità invio...")
break
ser = None
try:
mode = ""
while mode not in ["r", "s", "g"]:
@@ -170,5 +171,5 @@ except KeyboardInterrupt:
except serial.SerialException as e:
print(f"Errore nella connessione seriale: {e}")
finally:
if 'ser' in locals() and ser.is_open:
if ser is not None and ser.is_open:
ser.close()

222
LAB3/vivado/diligent_jstk/diligent_jstk.xpr
View File

@@ -77,29 +77,48 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../design/diligent_jstk/diligent_jstk.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/jstk_uart_bridge.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/diligent_jstk/diligent_jstk.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_jstk_uart_bridge_0_0/diligent_jstk_jstk_uart_bridge_0_0.xci">
<Proxy FileSetName="diligent_jstk_jstk_uart_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_clk_wiz_0_0/diligent_jstk_clk_wiz_0_0.xci">
<Proxy FileSetName="diligent_jstk_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_axi4stream_spi_master_0_0/diligent_jstk_axi4stream_spi_master_0_0.xci">
<Proxy FileSetName="diligent_jstk_axi4stream_spi_master_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_digilent_jstk2_0_0/diligent_jstk_digilent_jstk2_0_0.xci">
<Proxy FileSetName="diligent_jstk_digilent_jstk2_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_proc_sys_reset_0_0/diligent_jstk_proc_sys_reset_0_0.xci">
<Proxy FileSetName="diligent_jstk_proc_sys_reset_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_system_ila_0_0/diligent_jstk_system_ila_0_0.xci">
<Proxy FileSetName="diligent_jstk_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_AXI4Stream_UART_0_0/diligent_jstk_AXI4Stream_UART_0_0.xci">
<Proxy FileSetName="diligent_jstk_AXI4Stream_UART_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -145,9 +164,9 @@
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_proc_sys_reset_0_0" RelGenDir="$PGENDIR/diligent_jstk_proc_sys_reset_0_0">
<FileSet Name="diligent_jstk_jstk_uart_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_jstk_uart_bridge_0_0" RelGenDir="$PGENDIR/diligent_jstk_jstk_uart_bridge_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_proc_sys_reset_0_0"/>
<Option Name="TopModule" Val="diligent_jstk_jstk_uart_bridge_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -163,27 +182,27 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_system_ila_0_0" RelGenDir="$PGENDIR/diligent_jstk_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_digilent_jstk2_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_digilent_jstk2_0_0" RelGenDir="$PGENDIR/diligent_jstk_digilent_jstk2_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_digilent_jstk2_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/diligent_jstk_AXI4Stream_UART_0_0">
<FileSet Name="diligent_jstk_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_proc_sys_reset_0_0" RelGenDir="$PGENDIR/diligent_jstk_proc_sys_reset_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_AXI4Stream_UART_0_0"/>
<Option Name="TopModule" Val="diligent_jstk_proc_sys_reset_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_jstk_uart_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_jstk_uart_bridge_0_0" RelGenDir="$PGENDIR/diligent_jstk_jstk_uart_bridge_0_0">
<FileSet Name="diligent_jstk_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_system_ila_0_0" RelGenDir="$PGENDIR/diligent_jstk_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_jstk_uart_bridge_0_0"/>
<Option Name="TopModule" Val="diligent_jstk_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="diligent_jstk_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/diligent_jstk_AXI4Stream_UART_0_0">
<Config>
<Option Name="TopModule" Val="diligent_jstk_AXI4Stream_UART_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
@@ -207,79 +226,101 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_synth_1">
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_jstk_uart_bridge_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_0_synth_1">
<Run Id="diligent_jstk_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_axi4stream_spi_master_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_synth_1">
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_axi4stream_spi_master_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_system_ila_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_synth_1">
<Run Id="diligent_jstk_digilent_jstk2_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_digilent_jstk2_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_digilent_jstk2_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_digilent_jstk2_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_digilent_jstk2_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_digilent_jstk2_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_digilent_jstk2_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_digilent_jstk2_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_digilent_jstk2_0_0_synth_1">
<Run Id="diligent_jstk_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_synth_1">
<Run Id="diligent_jstk_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_system_ila_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_jstk_uart_bridge_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_synth_1">
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@@ -292,13 +333,16 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_impl_1">
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -315,7 +359,9 @@
</Run>
<Run Id="diligent_jstk_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -332,24 +378,9 @@
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -366,7 +397,47 @@
</Run>
<Run Id="diligent_jstk_digilent_jstk2_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_digilent_jstk2_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_digilent_jstk2_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_digilent_jstk2_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -383,24 +454,9 @@
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>

6
LAB3/vivado/lab3/lab3.xpr
View File

@@ -247,16 +247,17 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@@ -269,6 +270,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>

6
requirements.txt Normal file
View File

@@ -0,0 +1,6 @@
pyserial
matplotlib
pillow
numpy
tqdm
scipy