Lab 3: Audio Processing System #3
170
LAB3/sim/tb_balance_controller.vhd
Normal file
170
LAB3/sim/tb_balance_controller.vhd
Normal file
@@ -0,0 +1,170 @@
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----------------------------------------------------------------------------------
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-- Testbench for balance_controller
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY tb_balance_controller IS
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END tb_balance_controller;
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ARCHITECTURE Behavioral OF tb_balance_controller IS
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CONSTANT TDATA_WIDTH : POSITIVE := 24;
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CONSTANT BALANCE_WIDTH : POSITIVE := 10;
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CONSTANT BALANCE_STEP_2 : POSITIVE := 6;
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CONSTANT N_SAMPLES : INTEGER := 8;
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CONSTANT N_BALANCES : INTEGER := 5;
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COMPONENT balance_controller IS
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GENERIC (
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TDATA_WIDTH : POSITIVE := 24;
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BALANCE_WIDTH : POSITIVE := 10;
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BALANCE_STEP_2 : POSITIVE := 6
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);
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PORT (
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aclk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
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s_axis_tready : OUT STD_LOGIC;
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s_axis_tlast : IN STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC;
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balance : IN STD_LOGIC_VECTOR(BALANCE_WIDTH - 1 DOWNTO 0)
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);
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END COMPONENT;
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SIGNAL aclk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0);
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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SIGNAL balance : STD_LOGIC_VECTOR(BALANCE_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
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-- Test input samples
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TYPE sample_mem_type IS ARRAY(0 TO N_SAMPLES-1) OF STD_LOGIC_VECTOR(TDATA_WIDTH-1 DOWNTO 0);
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SIGNAL sample_mem : sample_mem_type := (
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x"000100", -- +256
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x"FFFE00", -- -512
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x"000001", -- +1
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x"FFFFFF", -- -1 (2's comp)
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x"7FFFFF", -- max positive
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x"800000", -- max negative
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x"000A00", -- +2560
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x"FFF600" -- -2560
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);
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-- Balance values: left, center, right, slightly left, slightly right
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TYPE balance_mem_type IS ARRAY(0 TO N_BALANCES-1) OF STD_LOGIC_VECTOR(BALANCE_WIDTH-1 DOWNTO 0);
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SIGNAL balance_mem : balance_mem_type := (
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std_logic_vector(to_unsigned(0, BALANCE_WIDTH)), -- full left
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std_logic_vector(to_unsigned(480, BALANCE_WIDTH)), -- center
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std_logic_vector(to_unsigned(1023, BALANCE_WIDTH)), -- full right
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std_logic_vector(to_unsigned(240, BALANCE_WIDTH)), -- slightly left
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std_logic_vector(to_unsigned(800, BALANCE_WIDTH)) -- slightly right
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);
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BEGIN
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-- Clock generation
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aclk <= NOT aclk AFTER 5 ns;
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-- DUT instantiation
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uut: balance_controller
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GENERIC MAP (
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TDATA_WIDTH => TDATA_WIDTH,
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BALANCE_WIDTH => BALANCE_WIDTH,
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BALANCE_STEP_2 => BALANCE_STEP_2
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)
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PORT MAP (
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aclk => aclk,
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aresetn => aresetn,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tready => s_axis_tready,
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s_axis_tlast => s_axis_tlast,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast,
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balance => balance
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);
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-- Stimulus process
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stimulus : PROCESS
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BEGIN
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-- Reset
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WAIT FOR 10 ns;
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aresetn <= '1';
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WAIT UNTIL rising_edge(aclk);
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-- Set balance to center
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balance <= balance_mem(1);
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WAIT UNTIL rising_edge(aclk);
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-- Send all samples (center)
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FOR i IN 0 TO N_SAMPLES-1 LOOP
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s_axis_tdata <= sample_mem(i);
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s_axis_tvalid <= '1';
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IF i = N_SAMPLES-1 THEN
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s_axis_tlast <= '1';
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ELSE
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s_axis_tlast <= '0';
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END IF;
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready = '0' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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END LOOP;
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s_axis_tvalid <= '0';
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s_axis_tlast <= '0';
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-- Change balance to full left
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WAIT FOR 20 ns;
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balance <= balance_mem(0);
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-- Send one more sample (left)
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WAIT UNTIL rising_edge(aclk);
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s_axis_tdata <= x"000100";
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s_axis_tvalid <= '1';
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s_axis_tlast <= '1';
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WAIT UNTIL rising_edge(aclk);
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WHILE s_axis_tready = '0' LOOP
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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s_axis_tvalid <= '0';
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s_axis_tlast <= '0';
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-- Sweep through other balance values
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FOR i IN 2 TO N_BALANCES-1 LOOP
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WAIT FOR 20 ns;
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balance <= balance_mem(i);
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WAIT UNTIL rising_edge(aclk);
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END LOOP;
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-- Wait and finish
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WAIT FOR 100 ns;
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WAIT;
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END PROCESS;
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-- Optionally, block m_axis_tready to test backpressure
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PROCESS
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BEGIN
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WAIT FOR 60 ns;
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WAIT UNTIL rising_edge(aclk);
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m_axis_tready <= '0';
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WAIT FOR 20 ns;
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WAIT UNTIL rising_edge(aclk);
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m_axis_tready <= '1';
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WAIT;
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END PROCESS;
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END Behavioral;
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@@ -6,7 +6,7 @@ ENTITY balance_controller IS
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GENERIC (
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GENERIC (
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TDATA_WIDTH : POSITIVE := 24;
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TDATA_WIDTH : POSITIVE := 24;
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BALANCE_WIDTH : POSITIVE := 10;
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BALANCE_WIDTH : POSITIVE := 10;
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BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**VOLUME_STEP_2
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BALANCE_STEP_2 : POSITIVE := 6 -- i.e., balance_values_per_step = 2**BALANCE_STEP_2
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);
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);
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PORT (
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PORT (
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aclk : IN STD_LOGIC;
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aclk : IN STD_LOGIC;
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@@ -28,127 +28,91 @@ END balance_controller;
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ARCHITECTURE Behavioral OF balance_controller IS
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ARCHITECTURE Behavioral OF balance_controller IS
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CONSTANT CENTER_VALUE : INTEGER := 2 ** (BALANCE_WIDTH - 1) - 1; -- 511 per BALANCE_WIDTH=10
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CONSTANT BALANCE_STEPS : INTEGER := (2 ** (BALANCE_WIDTH - 1)) / (2 ** BALANCE_STEP_2) + 1;
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CONSTANT DEADZONE : INTEGER := 32; -- Deadzone da -32 a +32
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CONSTANT BAL_MID : INTEGER := 2 ** (BALANCE_WIDTH - 1); -- 512 for 10 bit
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CONSTANT MAX_SHIFT : INTEGER := TDATA_WIDTH - 1; -- Massimo shift possibile
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CONSTANT BLOCK_SIZE : INTEGER := 2 ** BALANCE_STEP_2;
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CONSTANT DEAD_ZONE : INTEGER := BLOCK_SIZE / 2;
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SIGNAL balance_signed : signed(BALANCE_WIDTH - 1 DOWNTO 0);
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SIGNAL left_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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SIGNAL shift_amount_left, shift_amount_right : NATURAL RANGE 0 TO MAX_SHIFT;
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SIGNAL right_channel : INTEGER RANGE 0 TO BALANCE_STEPS := 0;
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-- Registri di pipeline
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SIGNAL m_axis_tvalid_int : STD_LOGIC;
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SIGNAL audio_in_reg : signed(TDATA_WIDTH - 1 DOWNTO 0);
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SIGNAL tlast_reg : STD_LOGIC;
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SIGNAL valid_reg : STD_LOGIC;
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-- Segnali di controllo
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SIGNAL ready_int : STD_LOGIC;
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SIGNAL processing_active : STD_LOGIC;
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BEGIN
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BEGIN
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-- Convert balance input to signed (-512 to +511)
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-- Assigning the output signals
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balance_signed <= signed(balance);
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m_axis_tvalid <= m_axis_tvalid_int;
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s_axis_tready <= m_axis_tready AND aresetn;
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-- Calcolo dello shift amount con deadzone e scaling esponenziale
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-- Balance to exp
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PROCESS (balance_signed)
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VARIABLE centered_value : signed(BALANCE_WIDTH - 1 DOWNTO 0);
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VARIABLE abs_value : unsigned(BALANCE_WIDTH - 2 DOWNTO 0);
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VARIABLE exp_shift : INTEGER;
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BEGIN
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-- Centra il valore intorno a 0 (da -512 a +511 -> da -511 a +511)
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centered_value := balance_signed - to_signed(CENTER_VALUE, BALANCE_WIDTH);
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-- Inizializzazione
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shift_amount_left <= 0;
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shift_amount_right <= 0;
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-- Calcola il valore assoluto
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IF centered_value(BALANCE_WIDTH - 1) = '1' THEN -- negativo
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abs_value := unsigned(-centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
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ELSE
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abs_value := unsigned(centered_value(BALANCE_WIDTH - 2 DOWNTO 0));
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END IF;
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-- Applica deadzone e calcola shift
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IF centered_value > DEADZONE THEN
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-- Calcola lo shift per il canale sinistro (valori positivi)
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exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
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IF exp_shift > MAX_SHIFT THEN
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shift_amount_left <= MAX_SHIFT;
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ELSE
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shift_amount_left <= exp_shift;
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END IF;
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ELSIF centered_value <- DEADZONE THEN
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-- Calcola lo shift per il canale destro (valori negativi)
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exp_shift := (to_integer(abs_value) - DEADZONE) / 2 ** BALANCE_STEP_2 + 1;
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IF exp_shift > MAX_SHIFT THEN
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shift_amount_right <= MAX_SHIFT;
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ELSE
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shift_amount_right <= exp_shift;
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END IF;
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||||||
END IF;
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||||||
END PROCESS;
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||||||
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||||||
-- Il resto del codice rimane IDENTICO alla versione originale
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||||||
-- Logica di controllo AXI
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||||||
PROCESS (aclk)
|
PROCESS (aclk)
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||||||
VARIABLE temp : signed(TDATA_WIDTH + MAX_SHIFT - 1 DOWNTO 0);
|
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||||||
BEGIN
|
BEGIN
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||||||
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||||||
IF rising_edge(aclk) THEN
|
IF rising_edge(aclk) THEN
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||||||
|
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||||||
IF aresetn = '0' THEN
|
IF aresetn = '0' THEN
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||||||
-- Reset asincrono
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left_channel <= 0;
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||||||
valid_reg <= '0';
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right_channel <= 0;
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||||||
audio_in_reg <= (OTHERS => '0');
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||||||
tlast_reg <= '0';
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processing_active <= '0';
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||||||
ELSE
|
ELSE
|
||||||
-- Gestione del flusso dati
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-- Balance left and right channels
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||||||
IF ready_int = '1' THEN
|
IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN
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||||||
valid_reg <= '0';
|
left_channel <= to_integer((unsigned(balance) - (BAL_MID + DEAD_ZONE)) SRL BALANCE_STEP_2) + 1;
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||||||
|
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||||||
IF s_axis_tvalid = '1' THEN
|
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||||||
-- Registrazione degli ingressi
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||||||
audio_in_reg <= signed(s_axis_tdata);
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||||||
tlast_reg <= s_axis_tlast;
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||||||
valid_reg <= '1';
|
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||||||
processing_active <= '1';
|
|
||||||
ELSE
|
ELSE
|
||||||
processing_active <= '0';
|
left_channel <= 0;
|
||||||
END IF;
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
-- Elaborazione del dato (sempre attiva)
|
IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN
|
||||||
IF processing_active = '1' OR valid_reg = '1' THEN
|
right_channel <= to_integer(((BAL_MID - DEAD_ZONE) - unsigned(balance)) SRL BALANCE_STEP_2) + 1;
|
||||||
temp := resize(audio_in_reg, temp'length);
|
|
||||||
|
|
||||||
IF tlast_reg = '0' THEN
|
|
||||||
temp := shift_right(temp, shift_amount_left);
|
|
||||||
ELSE
|
ELSE
|
||||||
temp := shift_right(temp, shift_amount_right);
|
right_channel <= 0;
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
-- Saturazione
|
|
||||||
IF temp > 2 ** (TDATA_WIDTH - 1) - 1 THEN
|
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(2 ** (TDATA_WIDTH - 1) - 1, TDATA_WIDTH));
|
|
||||||
ELSIF temp <- 2 ** (TDATA_WIDTH - 1) THEN
|
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(-2 ** (TDATA_WIDTH - 1), TDATA_WIDTH));
|
|
||||||
ELSE
|
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(temp(TDATA_WIDTH - 1 DOWNTO 0));
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
m_axis_tlast <= tlast_reg;
|
|
||||||
END IF;
|
|
||||||
END IF;
|
|
||||||
END IF;
|
END IF;
|
||||||
|
|
||||||
END PROCESS;
|
END PROCESS;
|
||||||
|
|
||||||
-- Logica combinazionale per tready
|
-- Handle AXIS stream
|
||||||
ready_int <= m_axis_tready OR NOT valid_reg;
|
PROCESS (aclk)
|
||||||
s_axis_tready <= ready_int;
|
BEGIN
|
||||||
|
|
||||||
-- Assegnazione del valid in uscita
|
IF rising_edge(aclk) THEN
|
||||||
m_axis_tvalid <= valid_reg;
|
|
||||||
|
IF aresetn = '0' THEN
|
||||||
|
m_axis_tvalid_int <= '0';
|
||||||
|
m_axis_tlast <= '0';
|
||||||
|
m_axis_tdata <= (OTHERS => '0');
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
-- Default output signals
|
||||||
|
m_axis_tlast <= '0';
|
||||||
|
|
||||||
|
-- Clear valid flag when master interface is ready
|
||||||
|
IF m_axis_tready = '1' THEN
|
||||||
|
m_axis_tvalid_int <= '0';
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
-- Handle the data flow
|
||||||
|
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
||||||
|
-- Joystick datasheet: (x-axis) a 0 value corresponds to the axis
|
||||||
|
-- being tilted fully to the left and a value of 1023
|
||||||
|
-- corresponds fully to the right
|
||||||
|
IF s_axis_tlast = '0' THEN -- left
|
||||||
|
m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), left_channel));
|
||||||
|
ELSE -- right
|
||||||
|
m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(signed(s_axis_tdata), right_channel));
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
m_axis_tvalid_int <= '1';
|
||||||
|
m_axis_tlast <= s_axis_tlast;
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
END IF;
|
||||||
|
|
||||||
|
END PROCESS;
|
||||||
|
|
||||||
END Behavioral;
|
END Behavioral;
|
||||||
@@ -83,6 +83,8 @@ BEGIN
|
|||||||
-- Handle the data flow
|
-- Handle the data flow
|
||||||
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
|
||||||
-- Multiply the input data with the volume and assign to output
|
-- Multiply the input data with the volume and assign to output
|
||||||
|
-- Joystick datasheet: (y-axis) a value of 0 when it is tilted all the way down
|
||||||
|
-- and a value of 1023 when it is tilted all the way up
|
||||||
IF volume_exp_mult >= 0 THEN
|
IF volume_exp_mult >= 0 THEN
|
||||||
m_axis_tdata <= STD_LOGIC_VECTOR(
|
m_axis_tdata <= STD_LOGIC_VECTOR(
|
||||||
shift_left(
|
shift_left(
|
||||||
|
|||||||
214
LAB3/vivado/balance_controller/balance_controller.xpr
Normal file
214
LAB3/vivado/balance_controller/balance_controller.xpr
Normal file
@@ -0,0 +1,214 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2020.2 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Version="7" Minor="54" Path="C:/DESD/LAB3/vivado/balance_controller/balance_controller.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="9307f0faa63246faab8b6e3351afc999"/>
|
||||||
|
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirIES" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||||
|
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||||
|
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="DSABoardId" Val="basys3"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="14"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="31">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../../src/balance_controller.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="balance_controller"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<File Path="$PPRDIR/../../sim/tb_balance_controller.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PPRDIR/tb_balance_controller_behav.wcfg">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="tb_balance_controller"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_balance_controller_behav.wcfg"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="15">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board>
|
||||||
|
<Jumpers/>
|
||||||
|
</Board>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
@@ -0,0 +1,97 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<wave_config>
|
||||||
|
<wave_state>
|
||||||
|
</wave_state>
|
||||||
|
<db_ref_list>
|
||||||
|
<db_ref path="tb_balance_controller_behav.wdb" id="1">
|
||||||
|
<top_modules>
|
||||||
|
<top_module name="tb_balance_controller" />
|
||||||
|
</top_modules>
|
||||||
|
</db_ref>
|
||||||
|
</db_ref_list>
|
||||||
|
<zoom_setting>
|
||||||
|
<ZoomStartTime time="0fs"></ZoomStartTime>
|
||||||
|
<ZoomEndTime time="116601fs"></ZoomEndTime>
|
||||||
|
<Cursor1Time time="100200fs"></Cursor1Time>
|
||||||
|
</zoom_setting>
|
||||||
|
<column_width_setting>
|
||||||
|
<NameColumnWidth column_width="147"></NameColumnWidth>
|
||||||
|
<ValueColumnWidth column_width="98"></ValueColumnWidth>
|
||||||
|
</column_width_setting>
|
||||||
|
<WVObjectSize size="16" />
|
||||||
|
<wvobject fp_name="/tb_balance_controller/aclk" type="logic">
|
||||||
|
<obj_property name="ElementShortName">aclk</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">aclk</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/aresetn" type="logic">
|
||||||
|
<obj_property name="ElementShortName">aresetn</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">aresetn</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider22">
|
||||||
|
<obj_property name="label">Balance</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/balance" type="array">
|
||||||
|
<obj_property name="ElementShortName">balance[9:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">balance[9:0]</obj_property>
|
||||||
|
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/uut/left_shift" type="other">
|
||||||
|
<obj_property name="ElementShortName">left_shift</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">left_shift</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/uut/right_shift" type="other">
|
||||||
|
<obj_property name="ElementShortName">right_shift</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">right_shift</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider20">
|
||||||
|
<obj_property name="label">s_axis</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/s_axis_tdata" type="array">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/s_axis_tlast" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/s_axis_tvalid" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/s_axis_tready" type="logic">
|
||||||
|
<obj_property name="ElementShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject type="divider" fp_name="divider21">
|
||||||
|
<obj_property name="label">m_axis</obj_property>
|
||||||
|
<obj_property name="DisplayName">label</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/m_axis_tdata" type="array">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tdata[23:0]</obj_property>
|
||||||
|
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/m_axis_tlast" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/m_axis_tvalid" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
<wvobject fp_name="/tb_balance_controller/m_axis_tready" type="logic">
|
||||||
|
<obj_property name="ElementShortName">m_axis_tready</obj_property>
|
||||||
|
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
|
||||||
|
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||||
|
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||||
|
</wvobject>
|
||||||
|
</wave_config>
|
||||||
Reference in New Issue
Block a user