LAB3/design/diligent_jstk/diligent_jstk.bd

@@ -5,7 +5,7 @@
       "device": "xc7a35tcpg236-1",
       "name": "diligent_jstk",
       "rev_ctrl_bd_flag": "RevCtrlBdOff",
-      "synth_flow_mode": "None",
+      "synth_flow_mode": "Hierarchical",
       "tool_version": "2020.2",
       "validated": "true"
     },
@@ -71,7 +71,7 @@
       "proc_sys_reset_0": {
         "vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
         "xci_name": "diligent_jstk_proc_sys_reset_0_0",
-        "xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0_1\\diligent_jstk_proc_sys_reset_0_0.xci",
         "inst_hier_path": "proc_sys_reset_0",
         "parameters": {
           "RESET_BOARD_INTERFACE": {
@@ -99,7 +99,7 @@
       "AXI4Stream_UART_0": {
         "vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
         "xci_name": "diligent_jstk_AXI4Stream_UART_0_0",
-        "xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0_1\\diligent_jstk_AXI4Stream_UART_0_0.xci",
         "inst_hier_path": "AXI4Stream_UART_0",
         "parameters": {
           "UART_BAUD_RATE": {
@@ -116,7 +116,7 @@
       "jstk_uart_bridge_0": {
         "vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0",
         "xci_name": "diligent_jstk_jstk_uart_bridge_0_0",
-        "xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0_1\\diligent_jstk_jstk_uart_bridge_0_0.xci",
         "inst_hier_path": "jstk_uart_bridge_0",
         "reference_info": {
           "ref_type": "hdl",
@@ -330,7 +330,7 @@
       "axi4stream_spi_master_0": {
         "vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
         "xci_name": "diligent_jstk_axi4stream_spi_master_0_0",
-        "xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0_1\\diligent_jstk_axi4stream_spi_master_0_0.xci",
         "inst_hier_path": "axi4stream_spi_master_0",
         "parameters": {
           "c_sclkfreq": {
@@ -341,7 +341,7 @@
       "system_ila_0": {
         "vlnv": "xilinx.com:ip:system_ila:1.1",
         "xci_name": "diligent_jstk_system_ila_0_0",
-        "xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_system_ila_0_0_1\\diligent_jstk_system_ila_0_0.xci",
         "inst_hier_path": "system_ila_0",
         "parameters": {
           "C_MON_TYPE": {
@@ -377,7 +377,7 @@
       "digilent_jstk2_0": {
         "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
         "xci_name": "diligent_jstk_digilent_jstk2_0_0",
-        "xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci",
+        "xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0_1\\diligent_jstk_digilent_jstk2_0_0.xci",
         "inst_hier_path": "digilent_jstk2_0",
         "parameters": {
           "SPI_SCLKFREQ": {
@@ -591,6 +591,18 @@
       }
     },
     "interface_nets": {
+      "AXI4Stream_UART_0_M00_AXIS_RX": {
+        "interface_ports": [
+          "AXI4Stream_UART_0/M00_AXIS_RX",
+          "jstk_uart_bridge_0/s_axis"
+        ]
+      },
+      "axi4stream_spi_master_0_SPI_M": {
+        "interface_ports": [
+          "SPI_M_0",
+          "axi4stream_spi_master_0/SPI_M"
+        ]
+      },
       "AXI4Stream_UART_0_UART": {
         "interface_ports": [
           "usb_uart",
@@ -604,30 +616,18 @@
           "system_ila_0/SLOT_0_AXIS"
         ]
       },
+      "jstk_uart_bridge_0_m_axis": {
+        "interface_ports": [
+          "AXI4Stream_UART_0/S00_AXIS_TX",
+          "jstk_uart_bridge_0/m_axis"
+        ]
+      },
       "axi4stream_spi_master_0_M_AXIS": {
         "interface_ports": [
           "axi4stream_spi_master_0/M_AXIS",
           "digilent_jstk2_0/s_axis",
           "system_ila_0/SLOT_1_AXIS"
         ]
-      },
-      "axi4stream_spi_master_0_SPI_M": {
-        "interface_ports": [
-          "SPI_M_0",
-          "axi4stream_spi_master_0/SPI_M"
-        ]
-      },
-      "AXI4Stream_UART_0_M00_AXIS_RX": {
-        "interface_ports": [
-          "AXI4Stream_UART_0/M00_AXIS_RX",
-          "jstk_uart_bridge_0/s_axis"
-        ]
-      },
-      "jstk_uart_bridge_0_m_axis": {
-        "interface_ports": [
-          "AXI4Stream_UART_0/S00_AXIS_TX",
-          "jstk_uart_bridge_0/m_axis"
-        ]
       }
     },
     "nets": {

LAB3/design/diligent_jstk/diligent_jstk.bda

@@ -21,22 +21,22 @@
   <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
   <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
     <node id="n0">
+      <data key="VM">diligent_jstk</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n1">
       <data key="VH">2</data>
       <data key="VM">diligent_jstk</data>
       <data key="VT">VR</data>
     </node>
-    <node id="n1">
+    <node id="n2">
       <data key="TU">active</data>
       <data key="VH">2</data>
       <data key="VT">PM</data>
     </node>
-    <node id="n2">
+    <edge id="e0" source="n0" target="n1">
-      <data key="VM">diligent_jstk</data>
-      <data key="VT">BC</data>
-    </node>
-    <edge id="e0" source="n2" target="n0">
     </edge>
-    <edge id="e1" source="n0" target="n1">
+    <edge id="e1" source="n1" target="n2">
     </edge>
   </graph>
 </graphml>

LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd

@@ -1,7 +1,7 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Fri May 16 22:32:02 2025
+--Date        : Sat May 17 13:12:32 2025
 --Host        : DavideASUS running 64-bit major release  (build 9200)
 --Command     : generate_target diligent_jstk_wrapper.bd
 --Design      : diligent_jstk_wrapper

LAB3/src/digilent_jstk2.vhd

@@ -2,173 +2,178 @@ LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY digilent_jstk2 IS
-    GENERIC (
+	GENERIC (
-        DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
+		DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
-        CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
+		CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
-        SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
+		SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
-    );
+	);
-    PORT (
+	PORT (
-        aclk : IN STD_LOGIC;
+		aclk : IN STD_LOGIC;
-        aresetn : IN STD_LOGIC;
+		aresetn : IN STD_LOGIC;
 
-        -- Data going TO the SPI IP-Core (and so, to the JSTK2 module)
+		-- Data going TO the SPI IP-Core (and so, to the JSTK2 module)
-        m_axis_tvalid : OUT STD_LOGIC;
+		m_axis_tvalid : OUT STD_LOGIC;
-        m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-        m_axis_tready : IN STD_LOGIC;
+		m_axis_tready : IN STD_LOGIC;
 
-        -- Data coming FROM the SPI IP-Core (and so, from the JSTK2 module)
+		-- Data coming FROM the SPI IP-Core (and so, from the JSTK2 module)
-        -- There is no tready signal, so you must be always ready to accept and use the incoming data, or it will be lost!
+		-- There is no tready signal, so you must be always ready to accept and use the incoming data, or it will be lost!
-        s_axis_tvalid : IN STD_LOGIC;
+		s_axis_tvalid : IN STD_LOGIC;
-        s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
 
-        -- Joystick and button values read from the module
+		-- Joystick and button values read from the module
-        jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		jstk_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-        jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		jstk_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-        btn_jstk : OUT STD_LOGIC;
+		btn_jstk : OUT STD_LOGIC;
-        btn_trigger : OUT STD_LOGIC;
+		btn_trigger : OUT STD_LOGIC;
 
-        -- LED color to send to the module
+		-- LED color to send to the module
-        led_r : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		led_r : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-        led_g : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		led_g : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-        led_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
+		led_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
-    );
+	);
 END digilent_jstk2;
 
 ARCHITECTURE Behavioral OF digilent_jstk2 IS
 
-    -- Code for the SetLEDRGB command, see the JSTK2 datasheet.
+	-- Code for the SetLEDRGB command, see the JSTK2 datasheet.
-    CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84";
+	CONSTANT CMDSETLEDRGB : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"84";
 
-    -- Do not forget that you MUST wait a bit between two packets. See the JSTK2 datasheet (and the SPI IP-Core README).
+	-- Do not forget that you MUST wait a bit between two packets. See the JSTK2 datasheet (and the SPI IP-Core README).
-    ------------------------------------------------------------
+	------------------------------------------------------------
 
-    CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000);
+	CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000);
 
-    -- State machine states
+	-- State machine states
-    TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY, WAIT_READY);
+	TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
-    TYPE rx_state_type IS (JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
+	TYPE rx_state_type IS (JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
 
-    SIGNAL tx_state : tx_state_type := DELAY;
+	SIGNAL tx_state : tx_state_type := DELAY;
-    SIGNAL rx_state : rx_state_type := JSTK_X_LOW;
+	SIGNAL rx_state : rx_state_type := JSTK_X_LOW;
 
-    SIGNAL tx_delay_counter : INTEGER := 0;
+	SIGNAL tx_delay_counter : INTEGER := 0;
 
-    SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
 BEGIN
-    -- The SPI IP-Core is a slave, so we must set the m_axis_tvalid signal to '1' when we want to send data to it.
+	-- The SPI IP-Core is a slave, so we must set the m_axis_tvalid signal to '1' when we want to send data to it.
-    WITH tx_state SELECT m_axis_tvalid <=
+	WITH tx_state SELECT m_axis_tvalid <=
-        '0' WHEN DELAY,
+		'0' WHEN DELAY,
-        '1' WHEN OTHERS;
+		'1' WHEN SEND_CMD,
+		'1' WHEN SEND_RED,
+		'1' WHEN SEND_GREEN,
+		'1' WHEN SEND_BLUE,
+		'1' WHEN SEND_DUMMY;
 
-    -- TX FSM: invia un nuovo comando solo dopo che la risposta precedente <20> stata ricevuta (rx_done = '1')
+	-- Send the data to the SPI IP-Core based on the current state of the TX FSM
-    TX : PROCESS (aclk)
+	WITH tx_state SELECT m_axis_tdata <=
-    BEGIN
+		(OTHERS => '0') WHEN DELAY,
-        IF rising_edge(aclk) THEN
+		CMDSETLEDRGB WHEN SEND_CMD,
-            IF aresetn = '0' THEN
+		led_r WHEN SEND_RED,
-                tx_state <= DELAY;
+		led_g WHEN SEND_GREEN,
-                m_axis_tdata <= (OTHERS => '0');
+		led_b WHEN SEND_BLUE,
-                tx_delay_counter <= 0;
+		"01101000" WHEN SEND_DUMMY; -- Dummy byte
 
-            ELSE
+	-- TX FSM: invia un nuovo comando solo dopo che la risposta precedente <20> stata ricevuta (rx_done = '1')
+	TX : PROCESS (aclk)
+	BEGIN
+		IF rising_edge(aclk) THEN
+			IF aresetn = '0' THEN
 
-                CASE tx_state IS
+				tx_state <= DELAY;
+				m_axis_tdata <= (OTHERS => '0');
+				tx_delay_counter <= 0;
 
-                    WHEN DELAY =>
+			ELSE
-                        IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
-                            tx_delay_counter <= 0;
-                            tx_state <= SEND_CMD;
-                        ELSE
-                            tx_delay_counter <= tx_delay_counter + 1;
-                        END IF;
 
-                    WHEN SEND_CMD =>
+				CASE tx_state IS
-                        tx_state <= SEND_RED;
-                        m_axis_tdata <= CMDSETLEDRGB;
 
-                    WHEN SEND_RED =>
+					WHEN DELAY =>
-                        IF m_axis_tready = '1' THEN
+						IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
-                            m_axis_tdata <= led_r;
+							tx_delay_counter <= 0;
-                            tx_state <= SEND_GREEN;
+							tx_state <= SEND_CMD;
-                        END IF;
+						ELSE
+							tx_delay_counter <= tx_delay_counter + 1;
+						END IF;
 
-                    WHEN SEND_GREEN =>
+					WHEN SEND_CMD =>
-                        IF m_axis_tready = '1' THEN
+						IF m_axis_tready = '1' THEN
-                            m_axis_tdata <= led_g;
+							tx_state <= SEND_RED;
-                            tx_state <= SEND_BLUE;
+						END IF;
-                        END IF;
 
-                    WHEN SEND_BLUE =>
+					WHEN SEND_RED =>
-                        IF m_axis_tready = '1' THEN
+						IF m_axis_tready = '1' THEN
-                            m_axis_tdata <= led_b;
+							tx_state <= SEND_GREEN;
-                            tx_state <= SEND_DUMMY;
+						END IF;
-                        END IF;
 
-                    WHEN SEND_DUMMY =>
+					WHEN SEND_GREEN =>
-                        IF m_axis_tready = '1' THEN
+						IF m_axis_tready = '1' THEN
-                            m_axis_tdata <= "01101000"; -- Dummy byte
+							tx_state <= SEND_BLUE;
-                            tx_state <= WAIT_READY;
+						END IF;
-                        END IF;
 
-                    WHEN WAIT_READY =>
+					WHEN SEND_BLUE =>
-                        IF m_axis_tready = '1' THEN
+						IF m_axis_tready = '1' THEN
-                            m_axis_tdata <= "01000101"; -- Dummy byte not readed
+							tx_state <= SEND_DUMMY;
-                            tx_state <= DELAY;
+						END IF;
-                        END IF;
 
-                END CASE;
+					WHEN SEND_DUMMY =>
-            END IF;
+						IF m_axis_tready = '1' THEN
-        END IF;
+							tx_state <= DELAY;
-    END PROCESS TX;
+						END IF;
 
-    -- RX FSM: riceve 5 byte, aggiorna le uscite e segnala a TX FSM quando la risposta <20> completa
+				END CASE;
-    RX : PROCESS (aclk)
+			END IF;
-    BEGIN
+		END IF;
-        IF rising_edge(aclk) THEN
+	END PROCESS TX;
 
-            IF aresetn = '0' THEN
+	-- RX FSM: riceve 5 byte, aggiorna le uscite e segnala a TX FSM quando la risposta <20> completa
+	RX : PROCESS (aclk)
+	BEGIN
+		IF rising_edge(aclk) THEN
 
-                rx_state <= JSTK_X_LOW;
+			IF aresetn = '0' THEN
-                rx_cache <= (OTHERS => '0');
 
-            ELSE
+				rx_state <= JSTK_X_LOW;
+				rx_cache <= (OTHERS => '0');
 
-                CASE rx_state IS
+			ELSE
 
-                    WHEN JSTK_X_LOW =>
+				CASE rx_state IS
-                        IF s_axis_tvalid = '1' THEN
-                            rx_cache <= s_axis_tdata;
-                            rx_state <= JSTK_X_HIGH;
-                        END IF;
 
-                    WHEN JSTK_X_HIGH =>
+					WHEN JSTK_X_LOW =>
-                        IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' THEN
-                            jstk_x <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
+							rx_cache <= s_axis_tdata;
-                            rx_state <= JSTK_Y_LOW;
+							rx_state <= JSTK_X_HIGH;
-                        END IF;
+						END IF;
 
-                    WHEN JSTK_Y_LOW =>
+					WHEN JSTK_X_HIGH =>
-                        IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' THEN
-                            rx_cache <= s_axis_tdata;
+							jstk_x <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
-                            rx_state <= JSTK_Y_HIGH;
+							rx_state <= JSTK_Y_LOW;
-                        END IF;
+						END IF;
 
-                    WHEN JSTK_Y_HIGH =>
+					WHEN JSTK_Y_LOW =>
-                        IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' THEN
-                            jstk_y <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
+							rx_cache <= s_axis_tdata;
-                            rx_state <= BUTTONS;
+							rx_state <= JSTK_Y_HIGH;
-                        END IF;
+						END IF;
 
-                    WHEN BUTTONS =>
+					WHEN JSTK_Y_HIGH =>
-                        IF s_axis_tvalid = '1' THEN
+						IF s_axis_tvalid = '1' THEN
-                            btn_jstk <= s_axis_tdata(0);
+							jstk_y <= s_axis_tdata(1 DOWNTO 0) & rx_cache;
-                            btn_trigger <= s_axis_tdata(1);
+							rx_state <= BUTTONS;
-                            rx_state <= JSTK_X_LOW;
+						END IF;
-                        END IF;
 
-                END CASE;
+					WHEN BUTTONS =>
-            END IF;
+						IF s_axis_tvalid = '1' THEN
-        END IF;
+							btn_jstk <= s_axis_tdata(0);
-    END PROCESS RX;
+							btn_trigger <= s_axis_tdata(1);
+							rx_state <= JSTK_X_LOW;
+						END IF;
+
+				END CASE;
+			END IF;
+		END IF;
+	END PROCESS RX;
 
 END ARCHITECTURE;

LAB3/test/uart_viewer.py

@@ -40,18 +40,18 @@ def receive_graph_mode(ser):
             if ser.in_waiting >= CHUNK_SIZE:
                 data = ser.read(CHUNK_SIZE)
                 if len(data) >= 2:
-                    x = data[0]
+                    x = data[1]
-                    y = data[1]
+                    y = data[2]
                     q.put((x, y))
 
     reader_thread = threading.Thread(target=serial_reader, daemon=True)
     reader_thread.start()
 
-    latest_point = [0, 0]
+    latest_point = [64, 64]  # Punto iniziale al centro del grafico
     fig, ax = plt.subplots()
     sc = ax.scatter([latest_point[0]], [latest_point[1]])
-    ax.set_xlim(0, 255)
+    ax.set_xlim(0, 127)
-    ax.set_ylim(0, 255)
+    ax.set_ylim(0, 127)
     ax.set_xlabel("X")
     ax.set_ylabel("Y")
     ax.set_title("Coordinate in tempo reale")