LAB3/design/diligent_jstk/diligent_jstk.bd

@@ -84,8 +84,8 @@
       },
       "clk_wiz_0": {
         "vlnv": "xilinx.com:ip:clk_wiz:6.0",
-        "xci_name": "diligent_jstk_clk_wiz_0_1",
-        "xci_path": "ip\\diligent_jstk_clk_wiz_0_1\\diligent_jstk_clk_wiz_0_1.xci",
+        "xci_name": "diligent_jstk_clk_wiz_0_0",
+        "xci_path": "ip\\diligent_jstk_clk_wiz_0_0_1\\diligent_jstk_clk_wiz_0_0.xci",
         "inst_hier_path": "clk_wiz_0",
         "parameters": {
           "CLK_IN1_BOARD_INTERFACE": {
@@ -591,28 +591,17 @@
       }
     },
     "interface_nets": {
-      "axi4stream_spi_master_0_SPI_M": {
-        "interface_ports": [
-          "SPI_M_0",
-          "axi4stream_spi_master_0/SPI_M"
-        ]
-      },
       "AXI4Stream_UART_0_UART": {
         "interface_ports": [
           "usb_uart",
           "AXI4Stream_UART_0/UART"
         ]
       },
-      "jstk_uart_bridge_0_m_axis": {
+      "digilent_jstk2_0_m_axis": {
         "interface_ports": [
-          "AXI4Stream_UART_0/S00_AXIS_TX",
-          "jstk_uart_bridge_0/m_axis"
-        ]
-      },
-      "AXI4Stream_UART_0_M00_AXIS_RX": {
-        "interface_ports": [
-          "AXI4Stream_UART_0/M00_AXIS_RX",
-          "jstk_uart_bridge_0/s_axis"
+          "digilent_jstk2_0/m_axis",
+          "axi4stream_spi_master_0/S_AXIS",
+          "system_ila_0/SLOT_0_AXIS"
         ]
       },
       "axi4stream_spi_master_0_M_AXIS": {
@@ -622,11 +611,22 @@
           "system_ila_0/SLOT_1_AXIS"
         ]
       },
-      "digilent_jstk2_0_m_axis": {
+      "axi4stream_spi_master_0_SPI_M": {
         "interface_ports": [
-          "digilent_jstk2_0/m_axis",
-          "axi4stream_spi_master_0/S_AXIS",
-          "system_ila_0/SLOT_0_AXIS"
+          "SPI_M_0",
+          "axi4stream_spi_master_0/SPI_M"
+        ]
+      },
+      "AXI4Stream_UART_0_M00_AXIS_RX": {
+        "interface_ports": [
+          "AXI4Stream_UART_0/M00_AXIS_RX",
+          "jstk_uart_bridge_0/s_axis"
+        ]
+      },
+      "jstk_uart_bridge_0_m_axis": {
+        "interface_ports": [
+          "AXI4Stream_UART_0/S00_AXIS_TX",
+          "jstk_uart_bridge_0/m_axis"
         ]
       }
     },

LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd

@@ -1,8 +1,8 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Fri May 16 16:28:03 2025
---Host        : Davide-Samsung running 64-bit major release  (build 9200)
+--Date        : Fri May 16 22:32:02 2025
+--Host        : DavideASUS running 64-bit major release  (build 9200)
 --Command     : generate_target diligent_jstk_wrapper.bd
 --Design      : diligent_jstk_wrapper
 --Purpose     : IP block netlist

LAB3/test/uart_viewer.py

@@ -1,10 +1,10 @@
 import serial
 import serial.tools.list_ports
 import time
+import queue
+import threading
 import matplotlib.pyplot as plt
 import matplotlib.animation as animation
-import threading
-import queue
 
 # CONFIGURAZIONE
 BASYS3_PID = 0x6010
@@ -24,6 +24,14 @@ if not dev:
 PORT = dev
 
 def receive_mode(ser):
+    print("Modalità ricezione. Premi Ctrl+C per uscire.\n")
+    while True:
+        if ser.in_waiting >= CHUNK_SIZE:
+            data = ser.read(CHUNK_SIZE)
+            hex_bytes = ' '.join(f"{b:02X}" for b in data)
+            print(f"HH | {hex_bytes}")
+
+def receive_graph_mode(ser):
     print("Modalità ricezione e visualizzazione coordinate in tempo reale. Premi Ctrl+C per uscire.\n")
     q = queue.Queue()
 
@@ -39,9 +47,7 @@ def receive_mode(ser):
     reader_thread = threading.Thread(target=serial_reader, daemon=True)
     reader_thread.start()
 
-    # Start with a single point at (0,0)
     latest_point = [0, 0]
-
     fig, ax = plt.subplots()
     sc = ax.scatter([latest_point[0]], [latest_point[1]])
     ax.set_xlim(0, 255)
@@ -51,12 +57,11 @@ def receive_mode(ser):
     ax.set_title("Coordinate in tempo reale")
 
     def update(frame):
-        # Update only if new data is available
         while not q.empty():
             x, y = q.get()
             latest_point[0] = x
             latest_point[1] = y
-        sc.set_offsets([latest_point])  # Note the extra brackets!
+        sc.set_offsets([latest_point])
         return sc,
 
     ani = animation.FuncAnimation(fig, update, interval=30, blit=True)
@@ -89,8 +94,8 @@ def send_mode(ser):
 
 try:
     mode = ""
-    while mode not in ["r", "s", "4"]:
-        mode = input("Vuoi ricevere (r), inviare (s) ? [r/s]: ").strip().lower()
+    while mode not in ["r", "s", "g"]:
+        mode = input("Vuoi ricevere (r), inviare (s), o ricevere con grafico (g)? [r/s/g]: ").strip().lower()
 
     ser = serial.Serial(PORT, BAUDRATE, timeout=1)
     print(f"Aperta porta seriale: {PORT} a {BAUDRATE} baud.\n")
@@ -99,6 +104,8 @@ try:
         receive_mode(ser)
     elif mode == "s":
         send_mode(ser)
+    elif mode == "g":
+        receive_graph_mode(ser)
     else:
         print("Selezione non valida. Uscita...")
         ser.close()

LAB3/vivado/diligent_jstk/diligent_jstk.xpr

@@ -165,9 +165,7 @@
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -177,9 +175,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>