LAB3/src/digilent_jstk2.vhd

@@ -3,7 +3,9 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY digilent_jstk2 IS
 	GENERIC (
-		DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
+		DELAY_US : INTEGER := 225; -- Delay (in us) between two packets
+								   -- 25us Required by the SPI IP-Core doesn't work,
+								   -- it requires another SPI clock cycle
 		CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
 		SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
 	);