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Lab 3: Audio Processing System #3

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PickleRick merged 43 commits from LAB3 into main 2025-06-07 22:18:48 +02:00
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LAB3/src/digilent_jstk2.vhd
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@@ -3,7 +3,9 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY digilent_jstk2 IS ENTITY digilent_jstk2 IS
GENERIC ( GENERIC (
DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work DELAY_US : INTEGER := 225; -- Delay (in us) between two packets
-- 25us Required by the SPI IP-Core doesn't work,
-- it requires another SPI clock cycle
CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz) CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz) SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
); );