DigiLAB ip AXI4Stream_UART 1.1 M00_AXIS_RX TDATA m00_axis_rx_tdata TVALID m00_axis_rx_tvalid TREADY m00_axis_rx_tready WIZ_DATA_WIDTH 32 S00_AXIS_TX TDATA s00_axis_tx_tdata TVALID s00_axis_tx_tvalid TREADY s00_axis_tx_tready WIZ_DATA_WIDTH 32 M00_AXIS_RX_RST RST m00_axis_rx_aresetn POLARITY ACTIVE_LOW M00_AXIS_RX_CLK CLK m00_axis_rx_aclk ASSOCIATED_BUSIF M00_AXIS_RX ASSOCIATED_RESET m00_axis_rx_aresetn S00_AXIS_TX_RST RST s00_axis_tx_aresetn POLARITY ACTIVE_LOW S00_AXIS_TX_CLK CLK s00_axis_tx_aclk ASSOCIATED_BUSIF S00_AXIS_TX ASSOCIATED_RESET s00_axis_tx_aresetn reset RST rst POLARITY ACTIVE_HIGH ClockUART Clock used to calculate the delay for UART CLK clk_uart ASSOCIATED_BUSIF UART ASSOCIATED_RESET rst UART UART TxD UART_TX RxD UART_RX BOARD.ASSOCIATED_PARAM UART_BOARD_INTERFACE required xilinx_vhdlsynthesis Synthesis :vivado.xilinx.com:synthesis vhdl AXI4Stream_UART_v1_0 xilinx_vhdlsynthesis_view_fileset viewChecksum 47fd635e xilinx_vhdlbehavioralsimulation Simulation :vivado.xilinx.com:simulation vhdl AXI4Stream_UART_v1_0 xilinx_vhdlbehavioralsimulation_view_fileset viewChecksum 47fd635e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 5514ca69 bd_tcl Block Diagram :vivado.xilinx.com:block.diagram bd_tcl_view_fileset viewChecksum c55a27a0 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util viewChecksum 16e75233 xilinx_implementation Implementation :vivado.xilinx.com:implementation xilinx_implementation_view_fileset viewChecksum 5c730a16 clk_uart in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation rst in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation UART_TX out STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation UART_RX in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation m00_axis_rx_aclk in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation m00_axis_rx_aresetn in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation m00_axis_rx_tvalid out STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation m00_axis_rx_tdata out 7 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation m00_axis_rx_tready in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axis_tx_aclk in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axis_tx_aresetn in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axis_tx_tready out STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axis_tx_tdata in 7 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation s00_axis_tx_tvalid in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation UART_BAUD_RATE Rs232 Baud Rate 115200 UART_CLOCK_FREQUENCY Rs232 Clock Frequency 100000000 C_M00_AXIS_RX_TDATA_WIDTH C M00 Axis Rx Tdata Width 8 C_S00_AXIS_TX_TDATA_WIDTH C S00 Axis Tx Tdata Width 8 choice_list_23c37a81 2400 4800 9600 19200 38400 57600 115200 230400 460800 921600 1000000 1500000 2000000 choice_list_6fc15197 32 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW choice_list_d8920bdd 8 xilinx_vhdlsynthesis_view_fileset hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd vhdlSource hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd vhdlSource hdl/UART_Engine.vhd vhdlSource hdl/UART_Manager.vhd vhdlSource hdl/AXI4Stream_UART_v1_0.vhd vhdlSource CHECKSUM_dad462a3 xilinx_vhdlbehavioralsimulation_view_fileset hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd vhdlSource hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd vhdlSource hdl/UART_Engine.vhd vhdlSource hdl/UART_Manager.vhd vhdlSource hdl/AXI4Stream_UART_v1_0.vhd vhdlSource xilinx_xpgui_view_fileset xgui/AXI4Stream_UART_v1_1.tcl tclSource CHECKSUM_5514ca69 XGUI_VERSION_2 bd_tcl_view_fileset bd/bd.tcl tclSource xilinx_implementation_view_fileset utils/board/board.xit xit USED_IN_board USED_IN_implementation USED_IN_synthesis AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output Component_Name AXI4Stream_UART_v1_0 UART_BAUD_RATE Baud Rate 115200 UART_CLOCK_FREQUENCY Rs232 Clock Frequency 100000000 C_M00_AXIS_RX_TDATA_WIDTH C M00 Axis Rx Tdata Width 8 false C_S00_AXIS_TX_TDATA_WIDTH C S00 Axis Tx Tdata Width 8 USE_BOARD_FLOW false UART_BOARD_INTERFACE Custom virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu virtexuplus kintexuplus zynquplus kintexu /AXI_Peripheral AXI4-Stream UART XPM_FIFO 1 TimeEngineers:ip:AXI4Stream_UART:1.0 2021-01-15T12:00:01Z 2020.2