DigiLAB ip axi4stream_spi_master 1.0 aclk CLK aclk ASSOCIATED_BUSIF S_AXIS:M_AXIS ASSOCIATED_RESET SPI_M SCK_T sclk_t IO1_O miso_o SS_T cs_t IO0_O mosi_o SCK_I sclk_i SS_O cs_o IO0_T mosi_t IO1_T miso_t SCK_O sclk_o SS_I cs_i IO1_I miso_i IO0_I mosi_i S_AXIS TDATA s_axis_tdata TVALID s_axis_tvalid TREADY s_axis_tready M_AXIS TDATA m_axis_tdata TVALID m_axis_tvalid aresetn RST aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL ipi_axis_lw_spi_master xilinx_anylanguagesynthesis_view_fileset viewChecksum 4adf0ae8 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL ipi_axis_lw_spi_master xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 4adf0ae8 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 30ce0f94 aclk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tvalid in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 7 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tready out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 7 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cs_i in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cs_o out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cs_t out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sclk_i in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sclk_o out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sclk_t out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mosi_i in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mosi_o out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation mosi_t out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation miso_i in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation miso_o out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation miso_t out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation c_clkfreq C Clkfreq 100000000 c_sclkfreq C Sclkfreq 1000000 c_cpol C Cpol 0 c_cpha C Cpha 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_list_8af5a703 0 1 xilinx_anylanguagesynthesis_view_fileset hdl/axis_lw_spi_master.vhd vhdlSource hdl/spi_master_lightweight/rtl/lw_spi_master.vhd vhdlSource hdl/ipi_axis_lw_spi_master.vhd vhdlSource CHECKSUM_009490da xilinx_anylanguagebehavioralsimulation_view_fileset hdl/axis_lw_spi_master.vhd vhdlSource hdl/spi_master_lightweight/rtl/lw_spi_master.vhd vhdlSource hdl/ipi_axis_lw_spi_master.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axi4stream_spi_master_v1_0.tcl tclSource CHECKSUM_30ce0f94 XGUI_VERSION_2 Lightweight AXI4-Stream SPI Master c_clkfreq aclk Frequency (Hz) 100000000 c_sclkfreq Desired SCLK frequency 1000000 c_cpol CPOL 0 c_cpha CPHA 0 Component_Name lw_spi_master_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexuplus virtexuplusHBM kintexuplus zynquplus kintexu /UserIP AXI4-Stream SPI Master package_project 1 user.org:user:lw_spi_master:1.0 2022-03-31T09:18:07Z /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master /home/nicola/Documents/Vivado/IPs/ip_repo/axi4-stream-spi-master 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