DigiLAB ip axis_dual_i2s 1.0 m_axis TDATA m_axis_tdata TLAST m_axis_tlast TVALID m_axis_tvalid TREADY m_axis_tready s_axis TDATA s_axis_tdata TLAST s_axis_tlast TVALID s_axis_tvalid TREADY s_axis_tready aresetn RST aresetn POLARITY ACTIVE_LOW i2s_resetn RST i2s_resetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m_axis:s_axis ASSOCIATED_RESET aresetn i2s_clk CLK i2s_clk ASSOCIATED_RESET i2s_resetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axis_i2s_wrapper xilinx_anylanguagesynthesis_view_fileset viewChecksum 4daa8100 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axis_i2s_wrapper xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 4daa8100 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f6c69e0f i2s_clk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i2s_resetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 23 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tlast in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axis_tdata out 23 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 m_axis_tlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_mclk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_lrck out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_sclk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_sdout out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_mclk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_lrck out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sclk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sdin in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset hdl/axis_dual_i2s.v verilogSource hdl/axis_dual_i2s_wrapper.v verilogSource CHECKSUM_f786a01c xilinx_anylanguagebehavioralsimulation_view_fileset hdl/axis_dual_i2s.v verilogSource hdl/axis_dual_i2s_wrapper.v verilogSource xilinx_xpgui_view_fileset xgui/axis_dual_i2s_v1_0.tcl tclSource CHECKSUM_f6c69e0f XGUI_VERSION_2 AXI4-Stream to Dual I2S Component_Name axis_i2s_wrapper_v1_0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexuplus virtexuplusHBM kintexuplus zynquplus kintexu /Communication_&_Networking/Serial_Interfaces AXI4-Stream to Dual I2S package_project XPM_FIFO 3 user.org:user:axis_i2s_wrapper:1.0 2022-05-09T16:06:21Z /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s /home/nicola/Documents/axi4-stream-dual-i2s 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