129 lines
3.2 KiB
VHDL
129 lines
3.2 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 03/16/2025 04:23:36 PM
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-- Design Name:
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-- Module Name: img_conv_tb - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity img_conv_tb is
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-- Port ( );
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end img_conv_tb;
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architecture Behavioral of img_conv_tb is
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component img_conv is
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generic(
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LOG2_N_COLS: POSITIVE :=8;
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LOG2_N_ROWS: POSITIVE :=8
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);
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port (
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clk : in std_logic;
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aresetn : in std_logic;
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m_axis_tdata : out std_logic_vector(7 downto 0);
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m_axis_tvalid : out std_logic;
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m_axis_tready : in std_logic;
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m_axis_tlast : out std_logic;
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conv_addr: out std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
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conv_data: in std_logic_vector(6 downto 0);
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start_conv: in std_logic;
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done_conv: out std_logic
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);
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end component;
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constant LOG2_N_COLS: POSITIVE :=2;
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constant LOG2_N_ROWS: POSITIVE :=2;
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type mem_type is array(0 to (2**LOG2_N_COLS)*(2**LOG2_N_ROWS)-1) of std_logic_vector(6 downto 0);
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signal mem : mem_type := (0=>"0000001",others => (others => '0'));
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signal clk : std_logic :='0';
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signal aresetn : std_logic :='0';
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signal m_axis_tdata : std_logic_vector(7 downto 0);
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signal m_axis_tvalid : std_logic;
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signal m_axis_tready : std_logic;
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signal m_axis_tlast : std_logic;
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signal conv_addr: std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
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signal conv_data: std_logic_vector(6 downto 0);
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signal start_conv: std_logic;
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signal done_conv: std_logic;
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begin
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m_axis_tready<='1';
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clk <= not clk after 5 ns;
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process (clk)
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begin
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if(rising_edge(clk)) then
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conv_data<=mem(to_integer(unsigned(conv_addr)));
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end if;
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end process;
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img_conv_inst: img_conv
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generic map(
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LOG2_N_COLS => LOG2_N_COLS,
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LOG2_N_ROWS => LOG2_N_ROWS
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)
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port map(
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clk => clk,
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aresetn => aresetn,
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m_axis_tdata => m_axis_tdata,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast,
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conv_addr => conv_addr,
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conv_data => conv_data,
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start_conv => start_conv,
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done_conv => done_conv
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);
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process
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begin
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wait for 10 ns;
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aresetn<='1';
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wait until rising_edge(clk);
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start_conv<='1';
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wait until rising_edge(clk);
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start_conv<='0';
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wait;
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end process;
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end Behavioral;
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