75 lines
1.7 KiB
VHDL
75 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_led_blinker is
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end entity;
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architecture behavior of tb_led_blinker is
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-- Constants
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constant CLK_PERIOD_NS : time := 10 ns;
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constant BLINK_PERIOD_MS : integer := 1000;
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constant N_BLINKS : integer := 4;
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-- DUT signals
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signal clk : std_logic := '0';
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signal aresetn : std_logic := '0';
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signal start_blink : std_logic := '0';
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signal led : std_logic;
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begin
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-- Clock process
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clk_process : process
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begin
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while true loop
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clk <= not clk;
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wait for CLK_PERIOD_NS / 2;
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end loop;
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end process;
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-- Instantiate DUT
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uut: entity work.led_blinker
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generic map (
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CLK_PERIOD_NS => 10,
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BLINK_PERIOD_MS => BLINK_PERIOD_MS,
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N_BLINKS => N_BLINKS
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)
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port map (
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clk => clk,
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aresetn => aresetn,
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start_blink => start_blink,
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led => led
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);
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-- Stimulus process
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stimulus : process
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begin
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-- Reset
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aresetn <= '0';
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wait for 50 ns;
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aresetn <= '1';
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wait for 50 ns;
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-- Primo impulso di start_blink
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start_blink <= '1';
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wait for 10 ns;
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start_blink <= '0';
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-- Aspetta metà blinking, poi rilancia start_blink
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wait for 3 sec;
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-- Secondo impulso (durante blinking)
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start_blink <= '1';
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wait for 10 ns;
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start_blink <= '0';
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-- Aspetta che finisca tutto
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wait for 10 sec;
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-- Fine simulazione
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assert false report "Test completed." severity failure;
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end process;
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end architecture;
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