- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
Cd16d
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