Cd16d 460378cdaa Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality

2025-05-16 16:44:46 +02:00

..

cons

Add initial design files and project configuration for LAB3

2025-05-12 14:20:41 +02:00

design

Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

2025-05-16 16:43:45 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update VHDL and Python files for improved functionality and performance

2025-05-15 16:46:09 +02:00

src

Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality

2025-05-16 16:44:46 +02:00

test

Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

2025-05-16 16:43:45 +02:00

vivado

Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.

2025-05-16 16:43:45 +02:00