Cd16d
b11c65043f
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
59 lines
1.8 KiB
VHDL
59 lines
1.8 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Mon May 12 18:14:19 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target loopback_I2S_wrapper.bd
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--Design : loopback_I2S_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity loopback_I2S_wrapper is
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port (
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reset : in STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC
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);
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end loopback_I2S_wrapper;
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architecture STRUCTURE of loopback_I2S_wrapper is
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component loopback_I2S is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC
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);
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end component loopback_I2S;
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begin
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loopback_I2S_i: component loopback_I2S
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port map (
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reset => reset,
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rx_lrck_0 => rx_lrck_0,
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rx_mclk_0 => rx_mclk_0,
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rx_sclk_0 => rx_sclk_0,
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rx_sdin_0 => rx_sdin_0,
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sys_clock => sys_clock,
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tx_lrck_0 => tx_lrck_0,
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tx_mclk_0 => tx_mclk_0,
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tx_sclk_0 => tx_sclk_0,
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tx_sdout_0 => tx_sdout_0
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);
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end STRUCTURE;
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