185 lines
4.8 KiB
VHDL
185 lines
4.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 03/16/2025 04:23:36 PM
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-- Design Name:
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-- Module Name: img_conv_tb - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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USE IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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ENTITY img_conv_tb IS
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-- Port ( );
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END img_conv_tb;
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ARCHITECTURE Behavioral OF img_conv_tb IS
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COMPONENT img_conv IS
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GENERIC (
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LOG2_N_COLS : POSITIVE := 8;
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LOG2_N_ROWS : POSITIVE := 8
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);
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC;
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conv_addr : OUT STD_LOGIC_VECTOR(LOG2_N_COLS + LOG2_N_ROWS - 1 DOWNTO 0);
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conv_data : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
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start_conv : IN STD_LOGIC;
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done_conv : OUT STD_LOGIC
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);
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END COMPONENT;
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CONSTANT LOG2_N_COLS : POSITIVE := 2;
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CONSTANT LOG2_N_ROWS : POSITIVE := 2;
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TYPE mem_type IS ARRAY(0 TO (2 ** LOG2_N_COLS) * (2 ** LOG2_N_ROWS) - 1) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
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-- Fill memory with more varied values
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SIGNAL mem : mem_type := (
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0 => "0000001",
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1 => "0101010",
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2 => "0011100",
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3 => "1110001",
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4 => "0001011",
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5 => "0110110",
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6 => "1001001",
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7 => "1111111",
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8 => "0000111",
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9 => "0010010",
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10 => "0100101",
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11 => "0111000",
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12 => "1001100",
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13 => "1011011",
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14 => "1100110",
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15 => "1010101"
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);
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tready : STD_LOGIC;
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL conv_addr : STD_LOGIC_VECTOR(LOG2_N_COLS + LOG2_N_ROWS - 1 DOWNTO 0);
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SIGNAL conv_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
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SIGNAL start_conv : STD_LOGIC;
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SIGNAL done_conv : STD_LOGIC;
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SIGNAL tready_block_req : STD_LOGIC := '0';
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BEGIN
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-- m_axis_tready logic with blocking step
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PROCESS (clk)
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VARIABLE block_counter : INTEGER := 0;
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VARIABLE tready_blocked : BOOLEAN := FALSE;
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BEGIN
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IF rising_edge(clk) THEN
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IF tready_block_req = '1' AND NOT tready_blocked THEN
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tready_blocked := TRUE;
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block_counter := 0;
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END IF;
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IF tready_blocked THEN
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IF block_counter < 19 THEN
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m_axis_tready <= '0';
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block_counter := block_counter + 1;
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ELSE
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m_axis_tready <= '1';
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tready_blocked := FALSE;
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block_counter := 0;
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END IF;
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ELSE
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m_axis_tready <= '1';
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END IF;
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END IF;
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END PROCESS;
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clk <= NOT clk AFTER 5 ns;
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PROCESS (clk)
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BEGIN
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IF (rising_edge(clk)) THEN
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conv_data <= mem(to_integer(unsigned(conv_addr)));
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END IF;
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END PROCESS;
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img_conv_inst : img_conv
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GENERIC MAP(
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LOG2_N_COLS => LOG2_N_COLS,
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LOG2_N_ROWS => LOG2_N_ROWS
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)
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PORT MAP(
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clk => clk,
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aresetn => aresetn,
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m_axis_tdata => m_axis_tdata,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast,
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conv_addr => conv_addr,
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conv_data => conv_data,
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start_conv => start_conv,
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done_conv => done_conv
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);
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PROCESS
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BEGIN
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WAIT FOR 10 ns;
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aresetn <= '1';
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WAIT UNTIL rising_edge(clk);
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start_conv <= '1';
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WAIT UNTIL rising_edge(clk);
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start_conv <= '0';
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-- Wait some cycles, then request tready block for 10 cycles
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WAIT FOR 200 ns;
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tready_block_req <= '1';
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WAIT UNTIL rising_edge(clk);
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tready_block_req <= '0';
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WAIT FOR 300 ns;
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tready_block_req <= '1';
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WAIT UNTIL rising_edge(clk);
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tready_block_req <= '0';
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WAIT FOR 200 ns;
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tready_block_req <= '1';
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WAIT UNTIL rising_edge(clk);
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tready_block_req <= '0';
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WAIT;
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END PROCESS;
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END Behavioral; |