85 lines
1.9 KiB
VHDL
85 lines
1.9 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY tb_KittCarPWM IS
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END tb_KittCarPWM;
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ARCHITECTURE testbench OF tb_KittCarPWM IS
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-- Test constants
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CONSTANT CLK_PERIOD : TIME := 10 ns;
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CONSTANT RESET_TIME : TIME := 10*CLK_PERIOD;
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CONSTANT PERIOD : TIME := 10 ms;
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-- Signals
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL reset : STD_LOGIC := '0';
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SIGNAL sw : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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SIGNAL led : STD_LOGIC_VECTOR(15 DOWNTO 0);
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-- Device Under Test (DUT) instance
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COMPONENT KittCarPWM
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GENERIC (
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CLK_PERIOD_NS : POSITIVE := 10;
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MIN_KITT_CAR_STEP_MS : POSITIVE := 1;
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NUM_OF_SWS : INTEGER := 16;
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NUM_OF_LEDS : INTEGER := 16;
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TAIL_LENGTH : INTEGER := 4
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);
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PORT (
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reset : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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sw : IN STD_LOGIC_VECTOR(NUM_OF_SWS - 1 DOWNTO 0);
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led : OUT STD_LOGIC_VECTOR(NUM_OF_LEDS - 1 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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-- Connect DUT
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dut_KittCarPWM : KittCarPWM
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GENERIC MAP (
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CLK_PERIOD_NS => 10,
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MIN_KITT_CAR_STEP_MS => 1,
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NUM_OF_SWS => 16,
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NUM_OF_LEDS => 16,
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TAIL_LENGTH => 4
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)
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PORT MAP (
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reset => reset,
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clk => clk,
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sw => sw,
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led => led
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);
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-- Clock generation process
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clk <= not clk after CLK_PERIOD/2;
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-- Reset Process
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reset_wave :process
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begin
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reset <= '1';
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wait for RESET_TIME;
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reset <= not reset;
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wait;
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end process;
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-- Test process
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stim_proc : PROCESS
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BEGIN
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-- wait for reset
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sw <= "0000000000000000";
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WAIT FOR RESET_TIME;
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-- Start
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for I in 0 to 2**16-1 loop
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sw <= std_logic_vector(to_unsigned(I, 16));
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WAIT FOR PERIOD;
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end loop;
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-- End simulation
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WAIT;
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END PROCESS;
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END testbench;
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