Davide
5cabb20fdd
- Modified the graph structure in pak_depak.bda to correct node and edge connections. - Adjusted testbench for packetizer (tb_packetizer.vhd) to fix data values and packet sizes. - Enhanced packetizer.vhd to manage footer sending based on last signal. - Removed obsolete executable file LAB2-Test_new.exe. - Updated Python test script (test.py) to include new test case for depack > pack functionality and improved image handling. - Altered Vivado project files to reflect changes in simulation and synthesis settings. - Deleted unnecessary test executable and added new image for depack > pack testing.
41 lines
1.2 KiB
VHDL
41 lines
1.2 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Thu Apr 24 15:46:08 2025
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--Host : DavideASUS running 64-bit major release (build 9200)
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--Command : generate_target pak_depak_wrapper.bd
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--Design : pak_depak_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity pak_depak_wrapper is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end pak_depak_wrapper;
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architecture STRUCTURE of pak_depak_wrapper is
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component pak_depak is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component pak_depak;
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begin
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pak_depak_i: component pak_depak
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port map (
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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