Davide
5cabb20fdd
- Modified the graph structure in pak_depak.bda to correct node and edge connections. - Adjusted testbench for packetizer (tb_packetizer.vhd) to fix data values and packet sizes. - Enhanced packetizer.vhd to manage footer sending based on last signal. - Removed obsolete executable file LAB2-Test_new.exe. - Updated Python test script (test.py) to include new test case for depack > pack functionality and improved image handling. - Altered Vivado project files to reflect changes in simulation and synthesis settings. - Deleted unnecessary test executable and added new image for depack > pack testing.
559 lines
15 KiB
Plaintext
559 lines
15 KiB
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0x9157799052A71E23",
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"device": "xc7a35tcpg236-1",
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"name": "pak_depak",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "Hierarchical",
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"tool_version": "2020.2",
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"validated": "true"
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},
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"design_tree": {
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"proc_sys_reset_0": "",
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"clk_wiz_0": "",
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"AXI4Stream_UART_0": "",
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"depacketizer_0": "",
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"packetizer_0": ""
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},
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"interface_ports": {
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"usb_uart": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:uart_rtl:1.0"
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}
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},
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"ports": {
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"reset": {
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"type": "rst",
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"direction": "I",
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"value": "ACTIVE_HIGH"
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}
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}
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},
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"sys_clock": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"CLK_DOMAIN": {
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"value": "pak_depak_sys_clock",
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"value_src": "default"
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},
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"FREQ_HZ": {
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"value": "100000000"
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},
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"FREQ_TOLERANCE_HZ": {
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"value": "0",
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"value_src": "default"
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},
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"PHASE": {
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"value": "0.000"
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}
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}
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}
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},
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"components": {
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"proc_sys_reset_0": {
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"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
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"xci_name": "pak_depak_proc_sys_reset_0_0",
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"xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci",
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"inst_hier_path": "proc_sys_reset_0",
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"parameters": {
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"clk_wiz_0": {
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"vlnv": "xilinx.com:ip:clk_wiz:6.0",
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"xci_name": "pak_depak_clk_wiz_0_0",
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"xci_path": "ip\\pak_depak_clk_wiz_0_0\\pak_depak_clk_wiz_0_0.xci",
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"inst_hier_path": "clk_wiz_0",
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"parameters": {
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"CLK_IN1_BOARD_INTERFACE": {
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"value": "sys_clock"
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},
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"AXI4Stream_UART_0": {
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"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
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"xci_name": "pak_depak_AXI4Stream_UART_0_0",
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"xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci",
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"inst_hier_path": "AXI4Stream_UART_0",
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"parameters": {
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"UART_BOARD_INTERFACE": {
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"value": "usb_uart"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"depacketizer_0": {
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"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
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"xci_name": "pak_depak_depacketizer_0_0",
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"xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci",
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"inst_hier_path": "depacketizer_0",
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"reference_info": {
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"ref_type": "hdl",
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"ref_name": "depacketizer",
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"boundary_crc": "0x0"
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},
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"interface_ports": {
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"m_axis": {
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"mode": "Master",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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"parameters": {
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"TDATA_NUM_BYTES": {
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"value": "1",
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"value_src": "constant"
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},
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"TDEST_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TID_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TUSER_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TREADY": {
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"value": "1",
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"value_src": "constant"
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},
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"HAS_TSTRB": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TKEEP": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TLAST": {
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"value": "1",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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},
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"port_maps": {
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"TDATA": {
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"physical_name": "m_axis_tdata",
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"direction": "O",
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"left": "7",
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"right": "0"
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},
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"TLAST": {
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"physical_name": "m_axis_tlast",
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"direction": "O"
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},
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"TVALID": {
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"physical_name": "m_axis_tvalid",
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"direction": "O"
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},
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"TREADY": {
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"physical_name": "m_axis_tready",
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"direction": "I"
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}
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}
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},
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"s_axis": {
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"mode": "Slave",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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"parameters": {
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"TDATA_NUM_BYTES": {
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"value": "1",
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"value_src": "constant"
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},
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"TDEST_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TID_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TUSER_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TREADY": {
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"value": "1",
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"value_src": "constant"
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},
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"HAS_TSTRB": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TKEEP": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TLAST": {
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"value": "0",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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},
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"port_maps": {
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"TDATA": {
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"physical_name": "s_axis_tdata",
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"direction": "I",
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"left": "7",
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"right": "0"
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},
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"TVALID": {
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"physical_name": "s_axis_tvalid",
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"direction": "I"
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},
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"TREADY": {
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"physical_name": "s_axis_tready",
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"direction": "O"
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}
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}
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}
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},
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"ports": {
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"clk": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"ASSOCIATED_BUSIF": {
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"value": "m_axis:s_axis",
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"value_src": "constant"
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},
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"ASSOCIATED_RESET": {
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"value": "aresetn",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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}
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},
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"aresetn": {
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"type": "rst",
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"direction": "I",
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"parameters": {
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"POLARITY": {
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"value": "ACTIVE_LOW",
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"value_src": "constant"
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}
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}
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}
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}
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},
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"packetizer_0": {
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"vlnv": "xilinx.com:module_ref:packetizer:1.0",
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"xci_name": "pak_depak_packetizer_0_0",
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"xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
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"inst_hier_path": "packetizer_0",
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"reference_info": {
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"ref_type": "hdl",
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"ref_name": "packetizer",
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"boundary_crc": "0x0"
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},
|
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"interface_ports": {
|
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"m_axis": {
|
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"mode": "Master",
|
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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"parameters": {
|
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"TDATA_NUM_BYTES": {
|
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"value": "1",
|
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"value_src": "constant"
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},
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"TDEST_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TID_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TUSER_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TREADY": {
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"value": "1",
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"value_src": "constant"
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},
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"HAS_TSTRB": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TKEEP": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TLAST": {
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"value": "0",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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},
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"port_maps": {
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"TDATA": {
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"physical_name": "m_axis_tdata",
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"direction": "O",
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"left": "7",
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"right": "0"
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},
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"TVALID": {
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"physical_name": "m_axis_tvalid",
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"direction": "O"
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},
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"TREADY": {
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"physical_name": "m_axis_tready",
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"direction": "I"
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}
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}
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},
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"s_axis": {
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"mode": "Slave",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0",
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"parameters": {
|
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"TDATA_NUM_BYTES": {
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"value": "1",
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"value_src": "constant"
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},
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"TDEST_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TID_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"TUSER_WIDTH": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TREADY": {
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"value": "1",
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"value_src": "constant"
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},
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"HAS_TSTRB": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TKEEP": {
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"value": "0",
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"value_src": "constant"
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},
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"HAS_TLAST": {
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"value": "1",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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},
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"port_maps": {
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"TDATA": {
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"physical_name": "s_axis_tdata",
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"direction": "I",
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"left": "7",
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"right": "0"
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},
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"TLAST": {
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"physical_name": "s_axis_tlast",
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"direction": "I"
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},
|
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"TVALID": {
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"physical_name": "s_axis_tvalid",
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"direction": "I"
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},
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"TREADY": {
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"physical_name": "s_axis_tready",
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"direction": "O"
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}
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}
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}
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},
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"ports": {
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"clk": {
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"type": "clk",
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"direction": "I",
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"parameters": {
|
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"ASSOCIATED_BUSIF": {
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"value": "m_axis:s_axis",
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"value_src": "constant"
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},
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"ASSOCIATED_RESET": {
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"value": "aresetn",
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"value_src": "constant"
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},
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"FREQ_HZ": {
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"value": "100000000",
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"value_src": "ip_prop"
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},
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"PHASE": {
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"value": "0.0",
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"value_src": "ip_prop"
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},
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"CLK_DOMAIN": {
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"value": "/clk_wiz_0_clk_out1",
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"value_src": "ip_prop"
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}
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}
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},
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"aresetn": {
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"type": "rst",
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"direction": "I",
|
|
"parameters": {
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"POLARITY": {
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"value": "ACTIVE_LOW",
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"value_src": "constant"
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}
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}
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}
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}
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}
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},
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"interface_nets": {
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"AXI4Stream_UART_0_M00_AXIS_RX": {
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"interface_ports": [
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"AXI4Stream_UART_0/M00_AXIS_RX",
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"depacketizer_0/s_axis"
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]
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},
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"depacketizer_0_m_axis": {
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"interface_ports": [
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"depacketizer_0/m_axis",
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"packetizer_0/s_axis"
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]
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},
|
|
"packetizer_0_m_axis": {
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"interface_ports": [
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"packetizer_0/m_axis",
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"AXI4Stream_UART_0/S00_AXIS_TX"
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]
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|
},
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|
"AXI4Stream_UART_0_UART": {
|
|
"interface_ports": [
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"usb_uart",
|
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"AXI4Stream_UART_0/UART"
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]
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}
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},
|
|
"nets": {
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|
"reset_1": {
|
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"ports": [
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"reset",
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"proc_sys_reset_0/ext_reset_in",
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"clk_wiz_0/reset"
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]
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},
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"sys_clock_1": {
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"ports": [
|
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"sys_clock",
|
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"clk_wiz_0/clk_in1"
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|
]
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|
},
|
|
"clk_wiz_0_clk_out1": {
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|
"ports": [
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"clk_wiz_0/clk_out1",
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|
"AXI4Stream_UART_0/clk_uart",
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|
"proc_sys_reset_0/slowest_sync_clk",
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"AXI4Stream_UART_0/m00_axis_rx_aclk",
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"AXI4Stream_UART_0/s00_axis_tx_aclk",
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"depacketizer_0/clk",
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"packetizer_0/clk"
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]
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},
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|
"proc_sys_reset_0_peripheral_reset": {
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"ports": [
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"proc_sys_reset_0/peripheral_reset",
|
|
"AXI4Stream_UART_0/rst"
|
|
]
|
|
},
|
|
"clk_wiz_0_locked": {
|
|
"ports": [
|
|
"clk_wiz_0/locked",
|
|
"proc_sys_reset_0/dcm_locked"
|
|
]
|
|
},
|
|
"proc_sys_reset_0_peripheral_aresetn": {
|
|
"ports": [
|
|
"proc_sys_reset_0/peripheral_aresetn",
|
|
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
|
|
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
|
|
"depacketizer_0/aresetn",
|
|
"packetizer_0/aresetn"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
} |