Cd16d
60a8aa912d
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
80 lines
789 B
Plaintext
80 lines
789 B
Plaintext
# Vivado-specific files and directories to ignore
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# Vivado temporary files
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*.jou
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*.log
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*.str
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*.pb
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*.wdb
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*.xpa
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*.backup.*
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# Simulation and synthesis-generated files
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*.bit
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*.bin
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*.elf
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*.mcs
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*.mem
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*.prm
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*.tsi
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*.vcd
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*.vdi
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*.ltx
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*.xci
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*.dcp
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*.xsa
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*.xise
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*.ngc
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*.ngd
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*.ncd
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*.bgn
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*.blf
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*.unroutes
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*.rpx
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*.par
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*.twr
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*.twx
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*.ptwx
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*.mrp
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*.pcf
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*.qpf
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*.qsf
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*.qws
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*.wdf
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*.lpr
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*.bxml
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# Vivado project directories
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*.sim/
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*.cache/
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*.hw/
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*.gen/
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.hwdbg/
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*.ip_user_files/
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.webtalk/
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.xsim/
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.xil/
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.xilinx/
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*.runs/
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.xtclsh_history
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.fpga_editor.log
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.fpga_editor.jou
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vivado_pid*.str
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vivado*.backup.jou
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vivado*.backup.log
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# SDK workspace
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.sdk/
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# design files
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**/design/**/ipshared/
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**/design/**/ip/
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**/design/**/sim/
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**/design/**/synth/
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**/design/**/ui/
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**/design/**/hw_handoff/
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# Other files
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**/test/*.zip |