Cd16d 82d76e48d8 Add comments

2025-05-27 17:42:40 +02:00

..

balance_controller

Refactor balance_controller and volume_multiplier for improved readability; update simulation settings in project files

2025-05-22 16:31:10 +02:00

diligent_jstk

Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

2025-05-19 16:24:36 +02:00

lab3

Fix LFO

2025-05-27 14:18:46 +02:00

LFO

Add comments

2025-05-27 17:42:40 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

moving_average_filter

Update to work at 180MHz

2025-05-26 14:08:08 +02:00

volume_multiplier

Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic

2025-05-23 11:12:07 +02:00

volume_saturator

Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic

2025-05-23 11:12:07 +02:00