Davide
835b4d0ab8
- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references. - Modified pak_depak_wrapper.vhd to reflect the correct timestamp. - Rearranged the order of components in pak_depak.bd for clarity and consistency. - Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity. - Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception. - Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments. - Improved img_conv.vhd with better state management and comments for the convolution process. - Updated led_blinker.vhd to enhance readability and maintainability with clearer comments. - Enhanced packetizer.vhd to improve data handling and added comments for better understanding. - Adjusted rgb2gray.vhd to include standard library comments for consistency. - Updated test.py to improve image processing logic and added visualization for differences. - Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak. - Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
50 lines
1.4 KiB
VHDL
50 lines
1.4 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
|
----------------------------------------------------------------------------------
|
|
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
|
|
--Date : Fri Apr 25 00:08:55 2025
|
|
--Host : DavideASUS running 64-bit major release (build 9200)
|
|
--Command : generate_target lab_2_wrapper.bd
|
|
--Design : lab_2_wrapper
|
|
--Purpose : IP block netlist
|
|
----------------------------------------------------------------------------------
|
|
library IEEE;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
library UNISIM;
|
|
use UNISIM.VCOMPONENTS.ALL;
|
|
entity lab_2_wrapper is
|
|
port (
|
|
led_of : out STD_LOGIC;
|
|
led_ok : out STD_LOGIC;
|
|
led_uf : out STD_LOGIC;
|
|
reset : in STD_LOGIC;
|
|
sys_clock : in STD_LOGIC;
|
|
usb_uart_rxd : in STD_LOGIC;
|
|
usb_uart_txd : out STD_LOGIC
|
|
);
|
|
end lab_2_wrapper;
|
|
|
|
architecture STRUCTURE of lab_2_wrapper is
|
|
component lab_2 is
|
|
port (
|
|
led_of : out STD_LOGIC;
|
|
led_ok : out STD_LOGIC;
|
|
led_uf : out STD_LOGIC;
|
|
sys_clock : in STD_LOGIC;
|
|
reset : in STD_LOGIC;
|
|
usb_uart_txd : out STD_LOGIC;
|
|
usb_uart_rxd : in STD_LOGIC
|
|
);
|
|
end component lab_2;
|
|
begin
|
|
lab_2_i: component lab_2
|
|
port map (
|
|
led_of => led_of,
|
|
led_ok => led_ok,
|
|
led_uf => led_uf,
|
|
reset => reset,
|
|
sys_clock => sys_clock,
|
|
usb_uart_rxd => usb_uart_rxd,
|
|
usb_uart_txd => usb_uart_txd
|
|
);
|
|
end STRUCTURE;
|