Davide
835b4d0ab8
- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references. - Modified pak_depak_wrapper.vhd to reflect the correct timestamp. - Rearranged the order of components in pak_depak.bd for clarity and consistency. - Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity. - Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception. - Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments. - Improved img_conv.vhd with better state management and comments for the convolution process. - Updated led_blinker.vhd to enhance readability and maintainability with clearer comments. - Enhanced packetizer.vhd to improve data handling and added comments for better understanding. - Adjusted rgb2gray.vhd to include standard library comments for consistency. - Updated test.py to improve image processing logic and added visualization for differences. - Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak. - Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
41 lines
1.2 KiB
VHDL
41 lines
1.2 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Thu Apr 24 19:38:15 2025
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--Host : DavideASUS running 64-bit major release (build 9200)
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--Command : generate_target pak_depak_wrapper.bd
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--Design : pak_depak_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity pak_depak_wrapper is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end pak_depak_wrapper;
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architecture STRUCTURE of pak_depak_wrapper is
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component pak_depak is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component pak_depak;
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begin
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pak_depak_i: component pak_depak
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port map (
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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