Davide 360ae72198 Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd

2025-04-09 11:40:21 +02:00

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pins.xdc

Add new VHDL entities for image processing and update test scripts for Lab2

2025-03-29 00:50:32 +01:00