104 lines
2.3 KiB
VHDL
104 lines
2.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ipi_axis_lw_spi_master is
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generic (
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c_clkfreq : integer := 100_000_000;
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c_sclkfreq : integer := 1_000_000;
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c_cpol : integer range 0 to 1 := 0;
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c_cpha : integer range 0 to 1 := 0
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);
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Port (
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aclk : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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s_axis_tvalid : in STD_LOGIC;
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s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
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s_axis_tready : out STD_LOGIC;
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m_axis_tvalid : out STD_LOGIC;
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m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
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cs_i : in STD_LOGIC;
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cs_o : out STD_LOGIC;
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cs_t : out STD_LOGIC;
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sclk_i : in STD_LOGIC;
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sclk_o : out STD_LOGIC;
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sclk_t : out STD_LOGIC;
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mosi_i : in STD_LOGIC;
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mosi_o : out STD_LOGIC;
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mosi_t : out STD_LOGIC;
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miso_i : in STD_LOGIC;
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miso_o : out STD_LOGIC;
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miso_t : out STD_LOGIC
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);
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end ipi_axis_lw_spi_master;
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architecture Behavioral of ipi_axis_lw_spi_master is
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component axis_lw_spi_master is
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generic (
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c_clkfreq : integer := 100_000_000;
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c_sclkfreq : integer := 1_000_000;
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c_cpol : std_logic := '0';
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c_cpha : std_logic := '0'
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);
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Port (
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aclk : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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s_axis_tvalid : in STD_LOGIC;
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s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
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s_axis_tready : out STD_LOGIC;
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m_axis_tvalid : out STD_LOGIC;
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m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
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cs : out STD_LOGIC;
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sclk : out STD_LOGIC;
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mosi : out STD_LOGIC;
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miso : in STD_LOGIC
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);
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end component;
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constant C_CPOL_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpol, 1));
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constant C_CPHA_SLV : std_logic_vector := std_logic_vector(to_unsigned(c_cpha, 1));
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begin
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inst_axis_lw_spi_master : axis_lw_spi_master
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generic map (
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c_clkfreq => c_clkfreq,
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c_sclkfreq => c_sclkfreq,
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c_cpol => C_CPOL_SLV(0),
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c_cpha => C_CPHA_SLV(0)
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)
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Port map (
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aclk => aclk,
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aresetn => aresetn,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tready => s_axis_tready,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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cs => cs_o,
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sclk => sclk_o,
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mosi => mosi_o,
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miso => miso_i
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);
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cs_t <= '0';
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sclk_t <= '0';
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mosi_t <= '0';
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miso_t <= '1';
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miso_o <= '0';
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end Behavioral;
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