Davide
14a6be00d6
- Created a new loopback design file (loopback.bda) with nodes and edges defined in GraphML format. - Added a new Vivado project file for loopback (loopback.xpr) with updated configurations. - Introduced a new testbench for image convolution (img_conv_tb.vhd) in the simulation sources. - Updated the main project file (lab2.xpr) to reflect changes in source files and top module for simulation. - Removed obsolete project files (pak_depak.xpr.zip) and updated paths for existing source files.
41 lines
1.2 KiB
VHDL
41 lines
1.2 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Fri Apr 25 10:52:31 2025
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--Host : DavideASUS running 64-bit major release (build 9200)
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--Command : generate_target loopback_wrapper.bd
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--Design : loopback_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity loopback_wrapper is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end loopback_wrapper;
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architecture STRUCTURE of loopback_wrapper is
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component loopback is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component loopback;
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begin
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loopback_i: component loopback
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port map (
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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