Davide
d156d1c944
- Updated .gitignore to exclude virtual environment and additional test files. - Modified diligent_jstk.bd to reorganize interface nets for clarity. - Adjusted diligent_jstk.bda to correct node attributes and edges. - Revised diligent_jstk_wrapper.vhd to ensure proper port declarations. - Enhanced uart_viewer.py for improved image handling and serial connection checks. - Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations. - Added requirements.txt to specify project dependencies for Python packages.
117 lines
3.4 KiB
VHDL
117 lines
3.4 KiB
VHDL
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Fri May 30 13:56:20 2025
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--Host : DavideASUS running 64-bit major release (build 9200)
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--Command : generate_target diligent_jstk_wrapper.bd
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--Design : diligent_jstk_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity diligent_jstk_wrapper is
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port (
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SPI_M_0_io0_io : inout STD_LOGIC;
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SPI_M_0_io1_io : inout STD_LOGIC;
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SPI_M_0_sck_io : inout STD_LOGIC;
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SPI_M_0_ss_io : inout STD_LOGIC;
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end diligent_jstk_wrapper;
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architecture STRUCTURE of diligent_jstk_wrapper is
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component diligent_jstk is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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SPI_M_0_sck_t : out STD_LOGIC;
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SPI_M_0_io1_o : out STD_LOGIC;
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SPI_M_0_ss_t : out STD_LOGIC;
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SPI_M_0_io0_o : out STD_LOGIC;
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SPI_M_0_sck_i : in STD_LOGIC;
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SPI_M_0_ss_o : out STD_LOGIC;
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SPI_M_0_io0_t : out STD_LOGIC;
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SPI_M_0_io1_t : out STD_LOGIC;
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SPI_M_0_sck_o : out STD_LOGIC;
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SPI_M_0_ss_i : in STD_LOGIC;
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SPI_M_0_io1_i : in STD_LOGIC;
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SPI_M_0_io0_i : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component diligent_jstk;
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component IOBUF is
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port (
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I : in STD_LOGIC;
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O : out STD_LOGIC;
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T : in STD_LOGIC;
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IO : inout STD_LOGIC
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);
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end component IOBUF;
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signal SPI_M_0_io0_i : STD_LOGIC;
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signal SPI_M_0_io0_o : STD_LOGIC;
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signal SPI_M_0_io0_t : STD_LOGIC;
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signal SPI_M_0_io1_i : STD_LOGIC;
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signal SPI_M_0_io1_o : STD_LOGIC;
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signal SPI_M_0_io1_t : STD_LOGIC;
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signal SPI_M_0_sck_i : STD_LOGIC;
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signal SPI_M_0_sck_o : STD_LOGIC;
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signal SPI_M_0_sck_t : STD_LOGIC;
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signal SPI_M_0_ss_i : STD_LOGIC;
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signal SPI_M_0_ss_o : STD_LOGIC;
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signal SPI_M_0_ss_t : STD_LOGIC;
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begin
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SPI_M_0_io0_iobuf: component IOBUF
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port map (
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I => SPI_M_0_io0_o,
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IO => SPI_M_0_io0_io,
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O => SPI_M_0_io0_i,
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T => SPI_M_0_io0_t
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);
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SPI_M_0_io1_iobuf: component IOBUF
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port map (
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I => SPI_M_0_io1_o,
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IO => SPI_M_0_io1_io,
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O => SPI_M_0_io1_i,
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T => SPI_M_0_io1_t
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);
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SPI_M_0_sck_iobuf: component IOBUF
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port map (
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I => SPI_M_0_sck_o,
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IO => SPI_M_0_sck_io,
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O => SPI_M_0_sck_i,
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T => SPI_M_0_sck_t
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);
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SPI_M_0_ss_iobuf: component IOBUF
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port map (
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I => SPI_M_0_ss_o,
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IO => SPI_M_0_ss_io,
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O => SPI_M_0_ss_i,
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T => SPI_M_0_ss_t
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);
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diligent_jstk_i: component diligent_jstk
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port map (
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SPI_M_0_io0_i => SPI_M_0_io0_i,
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SPI_M_0_io0_o => SPI_M_0_io0_o,
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SPI_M_0_io0_t => SPI_M_0_io0_t,
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SPI_M_0_io1_i => SPI_M_0_io1_i,
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SPI_M_0_io1_o => SPI_M_0_io1_o,
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SPI_M_0_io1_t => SPI_M_0_io1_t,
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SPI_M_0_sck_i => SPI_M_0_sck_i,
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SPI_M_0_sck_o => SPI_M_0_sck_o,
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SPI_M_0_sck_t => SPI_M_0_sck_t,
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SPI_M_0_ss_i => SPI_M_0_ss_i,
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SPI_M_0_ss_o => SPI_M_0_ss_o,
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SPI_M_0_ss_t => SPI_M_0_ss_t,
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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