176 lines
4.1 KiB
Verilog
176 lines
4.1 KiB
Verilog
`timescale 1ns / 1ps
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`default_nettype none
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module axis_i2s_wrapper (
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input wire i2s_clk, // require: approx 22.591MHz
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input wire i2s_resetn,
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input wire aclk,
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input wire aresetn,
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input wire [23:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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output wire [23:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire tx_mclk,
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output wire tx_lrck,
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output wire tx_sclk,
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output wire tx_sdout,
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output wire rx_mclk,
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output wire rx_lrck,
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output wire rx_sclk,
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input wire rx_sdin
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);
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wire [23:0] tx_axis_s_data;
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wire tx_axis_s_valid;
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wire tx_axis_s_ready;
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wire tx_axis_s_last;
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wire [23:0] rx_axis_m_data;
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wire rx_axis_m_valid;
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wire rx_axis_m_ready;
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wire rx_axis_m_last;
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xpm_fifo_axis #(
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.CDC_SYNC_STAGES(2),
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.CLOCKING_MODE("independent_clock"),
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.ECC_MODE("no_ecc"),
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.FIFO_DEPTH(1024),
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.FIFO_MEMORY_TYPE("auto"),
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.PACKET_FIFO("false"),
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.PROG_EMPTY_THRESH(10),
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.PROG_FULL_THRESH(10),
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.RD_DATA_COUNT_WIDTH(1),
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.RELATED_CLOCKS(0),
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.SIM_ASSERT_CHK(1),
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.TDATA_WIDTH(24),
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.TDEST_WIDTH(1),
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.TID_WIDTH(1),
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.TUSER_WIDTH(1),
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.USE_ADV_FEATURES("0000"),
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.WR_DATA_COUNT_WIDTH(1)
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)
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rx_fifo (
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.s_aclk(aclk),
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.s_aresetn(aresetn),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tdest(1'b0),
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.s_axis_tid(1'b0),
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.s_axis_tkeep(1'b111),
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.s_axis_tstrb(1'b111),
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.s_axis_tuser(1'b0),
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.m_aclk(i2s_clk),
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.m_axis_tvalid(tx_axis_s_valid),
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.m_axis_tready(tx_axis_s_ready),
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.m_axis_tdata(tx_axis_s_data),
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.m_axis_tlast(tx_axis_s_last),
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.m_axis_tdest(),
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.m_axis_tid(),
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.m_axis_tkeep(),
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.m_axis_tstrb(),
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.m_axis_tuser(),
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.almost_empty_axis(),
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.almost_full_axis(),
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.dbiterr_axis(),
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.prog_empty_axis(),
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.prog_full_axis(),
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.rd_data_count_axis(),
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.sbiterr_axis(),
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.wr_data_count_axis(),
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.injectdbiterr_axis(1'b0),
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.injectsbiterr_axis(1'b0)
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);
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axis_dual_i2s axis_dual_i2s_inst (
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.axis_clk(i2s_clk),
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.axis_resetn(i2s_resetn),
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.tx_axis_s_data(tx_axis_s_data),
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.tx_axis_s_valid(tx_axis_s_valid),
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.tx_axis_s_ready(tx_axis_s_ready),
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.tx_axis_s_last(tx_axis_s_last),
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.rx_axis_m_data(rx_axis_m_data),
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.rx_axis_m_valid(rx_axis_m_valid),
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.rx_axis_m_ready(rx_axis_m_ready),
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.rx_axis_m_last(rx_axis_m_last),
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.tx_mclk(tx_mclk),
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.tx_lrck(tx_lrck),
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.tx_sclk(tx_sclk),
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.tx_sdout(tx_sdout),
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.rx_mclk(rx_mclk),
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.rx_lrck(rx_lrck),
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.rx_sclk(rx_sclk),
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.rx_sdin(rx_sdin)
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);
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xpm_fifo_axis #(
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.CDC_SYNC_STAGES(2),
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.CLOCKING_MODE("independent_clock"),
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.ECC_MODE("no_ecc"),
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.FIFO_DEPTH(1024),
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.FIFO_MEMORY_TYPE("auto"),
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.PACKET_FIFO("false"),
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.PROG_EMPTY_THRESH(10),
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.PROG_FULL_THRESH(10),
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.RD_DATA_COUNT_WIDTH(1),
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.RELATED_CLOCKS(0),
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.SIM_ASSERT_CHK(1),
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.TDATA_WIDTH(24),
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.TDEST_WIDTH(1),
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.TID_WIDTH(1),
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.TUSER_WIDTH(1),
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.USE_ADV_FEATURES("0000"),
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.WR_DATA_COUNT_WIDTH(1)
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)
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tx_fifo (
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.s_aclk(i2s_clk),
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.s_aresetn(i2s_resetn),
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.s_axis_tvalid(rx_axis_m_valid),
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.s_axis_tready(rx_axis_m_ready),
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.s_axis_tdata(rx_axis_m_data),
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.s_axis_tlast(rx_axis_m_last),
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.s_axis_tdest(1'b0),
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.s_axis_tid(1'b0),
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.s_axis_tkeep(1'b111),
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.s_axis_tstrb(1'b111),
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.s_axis_tuser(1'b0),
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.m_aclk(aclk),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tdest(),
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.m_axis_tid(),
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.m_axis_tkeep(),
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.m_axis_tstrb(),
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.m_axis_tuser(),
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.almost_empty_axis(),
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.almost_full_axis(),
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.dbiterr_axis(),
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.prog_empty_axis(),
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.prog_full_axis(),
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.rd_data_count_axis(),
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.sbiterr_axis(),
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.wr_data_count_axis(),
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.injectdbiterr_axis(1'b0),
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.injectsbiterr_axis(1'b0)
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);
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endmodule
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