Davide aa01b3a6e2 Update clk

2025-05-26 18:41:47 +02:00

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diligent_jstk

Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

2025-05-19 16:24:36 +02:00

lab_3

Update clk

2025-05-26 18:41:47 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00