Cd16d aab2453819 Readd moving_average_filter_en

2025-05-19 16:33:35 +02:00

..

cons

Add initial design files and project configuration for LAB3

2025-05-12 14:20:41 +02:00

design

Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

2025-05-19 16:24:36 +02:00

ip

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

sim

Update VHDL and Python files for improved functionality and performance

2025-05-15 16:46:09 +02:00

src

Readd moving_average_filter_en

2025-05-19 16:33:35 +02:00

test

Refactor code structure for improved readability and maintainability

2025-05-17 20:03:03 +02:00

vivado

Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

2025-05-19 16:24:36 +02:00