Davide
d156d1c944
- Updated .gitignore to exclude virtual environment and additional test files. - Modified diligent_jstk.bd to reorganize interface nets for clarity. - Adjusted diligent_jstk.bda to correct node attributes and edges. - Revised diligent_jstk_wrapper.vhd to ensure proper port declarations. - Enhanced uart_viewer.py for improved image handling and serial connection checks. - Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations. - Added requirements.txt to specify project dependencies for Python packages.
87 lines
901 B
Plaintext
87 lines
901 B
Plaintext
# Vivado-specific files and directories to ignore
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# Vivado temporary files
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*.jou
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*.log
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*.str
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*.pb
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*.wdb
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*.xpa
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*.backup.*
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# Simulation and synthesis-generated files
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*.bit
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*.bin
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*.elf
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*.mcs
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*.mem
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*.prm
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*.tsi
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*.vcd
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*.vdi
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*.ltx
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*.xci
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*.dcp
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*.xsa
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*.xise
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*.ngc
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*.ngd
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*.ncd
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*.bgn
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*.blf
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*.unroutes
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*.rpx
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*.par
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*.twr
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*.twx
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*.ptwx
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*.mrp
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*.pcf
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*.qpf
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*.qsf
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*.qws
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*.wdf
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*.lpr
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*.bxml
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*.zip
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# Vivado project directories
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*.sim/
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*.cache/
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*.hw/
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*.gen/
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.hwdbg/
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*.ip_user_files/
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.webtalk/
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.xsim/
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.xil/
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.xilinx/
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*.runs/
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.xtclsh_history
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.fpga_editor.log
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.fpga_editor.jou
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vivado_pid*.str
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vivado*.backup.jou
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vivado*.backup.log
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# Directories to ignore
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.venv
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# SDK workspace
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.sdk/
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# design files
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**/design/**/ipshared/
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**/design/**/ip/
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**/design/**/sim/
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**/design/**/synth/
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**/design/**/ui/
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**/design/**/hw_handoff/
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**/design/**/*.xdc
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# Other files
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**/test/*.zip
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**/test/*.exe
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**/test/*.spec
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**/test/dist/
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**/test/build/ |