Cd16d
b11c65043f
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
37 lines
878 B
XML
37 lines
878 B
XML
<?xml version="1.0"?>
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<Index Version="1" Minor="0">
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<Repository value="/home/nicola/Documents/vivado/axi4-stream-uart">
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</Repository>
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<IP>
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<VLNV value="xilinx.com:user:AXI4Stream_UART:1.0">
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</VLNV>
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<DisplayName value="AXI4-Stream UART">
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</DisplayName>
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<Description value="AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output">
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</Description>
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<CoreRevision value="8">
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</CoreRevision>
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<ComponentPath value="component.xml">
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</ComponentPath>
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<Families>
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<Family name="artix7">
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<Part status="Production" name="ALL">
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</Part>
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</Family>
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<Family name="zynq">
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<Part status="Production" name="ALL">
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</Part>
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</Family>
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</Families>
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<Taxonomies>
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<Taxonomy value="AXI_Peripheral">
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</Taxonomy>
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</Taxonomies>
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<Interfaces>
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<Interface value="AXI4-Stream">
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</Interface>
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</Interfaces>
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</IP>
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</Index>
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