105 lines
2.2 KiB
VHDL
105 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity axis_lw_spi_master is
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generic (
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c_clkfreq : integer := 100_000_000;
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c_sclkfreq : integer := 1_000_000;
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c_cpol : std_logic := '0';
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c_cpha : std_logic := '0'
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);
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Port (
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aclk : in STD_LOGIC;
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aresetn : in STD_LOGIC;
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s_axis_tvalid : in STD_LOGIC;
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s_axis_tdata : in STD_LOGIC_VECTOR(7 downto 0);
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s_axis_tready : out STD_LOGIC;
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m_axis_tvalid : out STD_LOGIC;
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m_axis_tdata : out STD_LOGIC_VECTOR(7 downto 0);
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cs : out STD_LOGIC;
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sclk : out STD_LOGIC;
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mosi : out STD_LOGIC;
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miso : in STD_LOGIC
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);
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end axis_lw_spi_master;
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architecture Behavioral of axis_lw_spi_master is
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component lw_spi_master is
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generic (
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c_clkfreq : integer := 50_000_000;
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c_sclkfreq : integer := 5_000_000;
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c_cpol : std_logic := '0';
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c_cpha : std_logic := '0'
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);
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Port (
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clk_i : in STD_LOGIC;
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rst_i : in STD_LOGIC;
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en_i : in STD_LOGIC;
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mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
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miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
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data_ready_o : out STD_LOGIC;
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cs_o : out STD_LOGIC;
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sclk_o : out STD_LOGIC;
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mosi_o : out STD_LOGIC;
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miso_i : in STD_LOGIC
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);
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end component;
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signal rst : std_logic;
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signal data_ready : std_logic;
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signal data_ready_reg : std_logic;
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signal new_data : std_logic;
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begin
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inst_lw_spi_master : lw_spi_master
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generic map (
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c_clkfreq => c_clkfreq,
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c_sclkfreq => c_sclkfreq,
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c_cpol => c_cpol,
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c_cpha => c_cpha
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)
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Port map (
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clk_i => aclk,
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rst_i => rst,
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en_i => s_axis_tvalid,
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mosi_data_i => s_axis_tdata,
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miso_data_o => m_axis_tdata,
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data_ready_o => data_ready,
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cs_o => cs,
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sclk_o => sclk,
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mosi_o => mosi,
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miso_i => miso
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);
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rst <= not aresetn;
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s_axis_tready <= new_data;
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m_axis_tvalid <= new_data;
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process (aclk)
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begin
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if rising_edge(aclk) then
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if aresetn = '0' then
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new_data <= '0';
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else
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data_ready_reg <= data_ready;
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if data_ready_reg = '0' and data_ready = '1' then
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new_data <= '1';
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else
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new_data <= '0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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