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Code Issues 2 Pull Requests Releases Activity
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d4f2772027c5ed0425a79cfb19f48114a0c39c04
DESD/LAB3/sim
History
Davide d4f2772027 Update to work at 180MHz
2025-05-26 14:08:08 +02:00
..
tb_balance_controller.vhd
Add testbench for balance_controller and update Vivado project files
2025-05-22 11:22:57 +02:00
tb_digilent_jstk2.vhd
Update VHDL and Python files for improved functionality and performance
2025-05-15 16:46:09 +02:00
tb_LFO.vhd
Update to work at 180MHz
2025-05-26 14:08:08 +02:00
tb_moving_average.vhd
Add moving average filter testbench and configuration files; refactor signal handling in filter components
2025-05-23 12:49:46 +02:00
tb_volume_multiplier.vhd
Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic
2025-05-23 11:12:07 +02:00
tb_volume_saturator.vhd
Add Vivado project files and testbench configurations for volume multiplier and volume saturator
2025-05-21 00:31:23 +02:00
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