117 lines
3.8 KiB
VHDL
117 lines
3.8 KiB
VHDL
-- filepath: c:\DESD\LAB3\sim\tb_LFO.vhd
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_LFO IS
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END tb_LFO;
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ARCHITECTURE sim OF tb_LFO IS
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CONSTANT CHANNEL_LENGHT : INTEGER := 24;
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CONSTANT JOYSTICK_LENGHT : INTEGER := 10;
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CONSTANT TRIANGULAR_COUNTER_LENGHT: INTEGER := 10;
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CONSTANT CLK_PERIOD_NS : INTEGER := 10;
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SIGNAL aclk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL lfo_period : STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL lfo_enable : STD_LOGIC := '0';
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tlast : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
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SIGNAL m_axis_tlast : STD_LOGIC;
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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-- DUT
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COMPONENT LFO
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GENERIC (
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CHANNEL_LENGHT : INTEGER := 24;
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JOYSTICK_LENGHT : INTEGER := 10;
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CLK_PERIOD_NS : INTEGER := 10;
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TRIANGULAR_COUNTER_LENGHT : INTEGER := 10
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);
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PORT (
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aclk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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lfo_period : IN STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 DOWNTO 0);
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lfo_enable : IN STD_LOGIC;
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
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s_axis_tlast : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(CHANNEL_LENGHT-1 DOWNTO 0);
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m_axis_tlast : OUT STD_LOGIC;
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m_axis_tready : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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-- Clock generation
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clk_proc : PROCESS
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BEGIN
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aclk <= '0';
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WAIT FOR 5 ns;
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aclk <= '1';
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WAIT FOR 5 ns;
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END PROCESS;
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-- DUT instantiation
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dut: LFO
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GENERIC MAP (
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CHANNEL_LENGHT => CHANNEL_LENGHT,
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JOYSTICK_LENGHT => JOYSTICK_LENGHT,
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CLK_PERIOD_NS => CLK_PERIOD_NS,
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TRIANGULAR_COUNTER_LENGHT => TRIANGULAR_COUNTER_LENGHT
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)
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PORT MAP (
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aclk => aclk,
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aresetn => aresetn,
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lfo_period => lfo_period,
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lfo_enable => lfo_enable,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tdata => s_axis_tdata,
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s_axis_tlast => s_axis_tlast,
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s_axis_tready => s_axis_tready,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tdata => m_axis_tdata,
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m_axis_tlast => m_axis_tlast,
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m_axis_tready => m_axis_tready
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);
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-- Stimulus process
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stim_proc : PROCESS
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VARIABLE data_cnt : INTEGER := 0;
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BEGIN
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-- Reset
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aresetn <= '0';
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WAIT FOR 20 ns;
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aresetn <= '1';
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WAIT FOR 10 ns;
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-- Imposta parametri iniziali
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lfo_enable <= '1'; -- o '0' se vuoi testare la modalit<69> bypass
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lfo_period <= std_logic_vector(to_unsigned(512, JOYSTICK_LENGHT)); -- Valore fisso
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-- Loop infinito: invia dati ad ogni ciclo di clock
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WHILE TRUE LOOP
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WAIT UNTIL rising_edge(aclk);
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s_axis_tdata <= std_logic_vector(to_signed(data_cnt, CHANNEL_LENGHT));
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s_axis_tvalid <= '1';
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s_axis_tlast <= '0'; -- Puoi impostare a '1' ogni N campioni se vuoi testare tlast
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IF s_axis_tready = '1' THEN
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data_cnt := data_cnt + 1;
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END IF;
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END LOOP;
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END PROCESS;
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END sim; |