Cd16d fd7bac0da1 Refactor balance_controller and volume_multiplier for improved readability; update simulation settings in project files

2025-05-22 16:31:10 +02:00

..

balance_controller

Refactor balance_controller and volume_multiplier for improved readability; update simulation settings in project files

2025-05-22 16:31:10 +02:00

diligent_jstk

Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.

2025-05-19 16:24:36 +02:00

lab3

Add Vivado project files and testbench configurations for volume multiplier and volume saturator

2025-05-21 00:31:23 +02:00

loopback_I2S

Add AXI4-Stream UART IP and associated files

2025-05-12 18:16:58 +02:00

volume_multiplier

Refactor balance_controller and volume_multiplier for improved readability; update simulation settings in project files

2025-05-22 16:31:10 +02:00

volume_saturator

Add Vivado project files and testbench configurations for volume multiplier and volume saturator

2025-05-21 00:31:23 +02:00