Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files

LAB2/design/lab_2/hdl/lab_2_wrapper.vhd

@@ -1,7 +1,7 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Fri Apr 25 10:55:47 2025
+--Date        : Fri Apr 25 22:08:38 2025
 --Host        : DavideASUS running 64-bit major release  (build 9200)
 --Command     : generate_target lab_2_wrapper.bd
 --Design      : lab_2_wrapper

LAB2/design/lab_2/lab_2.bd

@@ -1169,6 +1169,13 @@
       }
     },
     "interface_nets": {
+      "rgb2gray_0_m_axis": {
+        "interface_ports": [
+          "rgb2gray_0/m_axis",
+          "bram_writer_0/s_axis",
+          "system_ila_0/SLOT_2_AXIS"
+        ]
+      },
       "img_conv_0_m_axis": {
         "interface_ports": [
           "img_conv_0/m_axis",
@@ -1200,13 +1207,6 @@
           "depacketizer_0/m_axis",
           "system_ila_0/SLOT_0_AXIS"
         ]
-      },
-      "rgb2gray_0_m_axis": {
-        "interface_ports": [
-          "rgb2gray_0/m_axis",
-          "bram_writer_0/s_axis",
-          "system_ila_0/SLOT_2_AXIS"
-        ]
       }
     },
     "nets": {

LAB2/design/lab_2/lab_2.bda

@@ -21,22 +21,22 @@
   <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
   <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
     <node id="n0">
-      <data key="VH">2</data>
-      <data key="VM">lab_2</data>
-      <data key="VT">VR</data>
-    </node>
-    <node id="n1">
       <data key="TU">active</data>
       <data key="VH">2</data>
       <data key="VT">PM</data>
     </node>
-    <node id="n2">
+    <node id="n1">
       <data key="VM">lab_2</data>
       <data key="VT">BC</data>
     </node>
-    <edge id="e0" source="n2" target="n0">
+    <node id="n2">
+      <data key="VH">2</data>
+      <data key="VM">lab_2</data>
+      <data key="VT">VR</data>
+    </node>
+    <edge id="e0" source="n1" target="n2">
     </edge>
-    <edge id="e1" source="n0" target="n1">
+    <edge id="e1" source="n2" target="n0">
     </edge>
   </graph>
 </graphml>

LAB2/src/divider_by_3.vhd

@@ -25,13 +25,13 @@ ARCHITECTURE Behavioral OF divider_by_3 IS
     SIGNAL mult_result : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
     SIGNAL sum_with_offset : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
 BEGIN
-    -- Moltiplicazione senza perdita di bit
+    -- Multiplication without loss of bits
     mult_result <= dividend * TO_UNSIGNED(DIVISION_MULTIPLIER, N - 1);
 
-    -- Somma con offset senza perdita di bit
+    -- Addition with offset, no loss of bits
     sum_with_offset <= mult_result + TO_UNSIGNED(OFFSET, MULT_WIDTH);
 
-    -- Estrazione risultato arrotondato
+    -- Extract rounded result
     result <= sum_with_offset(MULT_WIDTH - 2 DOWNTO MULT_WIDTH - BIT_DEPTH -1);
  
 END Behavioral;

LAB2/src/rgb2gray.vhd

@@ -50,12 +50,13 @@ ARCHITECTURE Behavioral OF rgb2gray IS
 
 BEGIN
 
+    -- Connect internal signals to output ports
     s_axis_tready <= s_axis_tready_int;
     m_axis_tvalid <= m_axis_tvalid_int;
     m_axis_tdata <= m_axis_tdata_int;
     m_axis_tlast <= m_axis_tlast_int;
 
-    -- Divider instance
+    -- Divider instance: divides the sum of RGB by 3 to obtain grayscale value
     DIVIDER : divider_by_3
     GENERIC MAP(
         BIT_DEPTH => 7
@@ -69,6 +70,7 @@ BEGIN
     BEGIN
         IF rising_edge(clk) THEN
             IF resetn = '0' THEN
+                -- Asynchronous reset: initialize all signals and state
                 state <= IDLE;
                 sum <= (OTHERS => '0');
                 rgb_sum <= (OTHERS => '0');
@@ -79,11 +81,12 @@ BEGIN
                 s_axis_tready_int <= '1';
                 last_seen <= '0';
             ELSE
-                -- Default assignments
+                -- Default assignments for each clock cycle
                 m_axis_tlast_int <= '0';
 
                 CASE state IS
                     WHEN IDLE =>
+                        -- Wait for the first valid input sample
                         m_axis_tdata_int <= (OTHERS => '0');
                         sum <= (OTHERS => '0');
                         count <= 0;
@@ -99,6 +102,7 @@ BEGIN
                         END IF;
 
                     WHEN ACCUMULATE =>
+                        -- Accumulate the next two color components (expecting 3 total: R, G, B)
                         IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
                             sum <= sum + unsigned(s_axis_tdata);
                             IF count = 2 THEN
@@ -117,7 +121,7 @@ BEGIN
                         END IF;
 
                     WHEN WAIT_DIV =>
-                        -- Ora gray <EFBFBD> valido
+                        -- Now gray is valid (output from divider)
                         m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray);
                         m_axis_tvalid_int <= '1';
                         s_axis_tready_int <= '0';
@@ -128,7 +132,7 @@ BEGIN
                         state <= SEND;
 
                     WHEN SEND =>
-                        -- Mantieni il dato finch<63> non viene accettato
+                        -- Hold the data until it is accepted by the downstream module
                         IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
                             m_axis_tvalid_int <= '0';
                             s_axis_tready_int <= '1';